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| OKI Semiconductor ML9051G GENERAL DESCRIPTION PEDL9051G-01 Issue Date: Jul. 23, 2002 Preliminary 132-Channel LCD Driver with Built-in RAM for LCD Dot Matrix Displays The ML9051G is an LSI for dot matrix graphic LCD devices carrying out bit map display. This LSI can drive a dot matrix graphic LCD display panel under the control of an 8-bit microcomputer (hereinafter described MPU). Since all the functions necessary for driving a bit map type LCD device are incorporated in a single chip, using the ML9051G makes it possible to realize a bit map type dot matrix graphic LCD display system with only a few chips. Since the bit map method in which one bit of display RAM data turns ON or OFF one dot in the display panel, it is possible to carry out displays with a high degree of freedom such as Chinese character displays, etc. With one chip, it is possible to construct a graphic display system with a maximum of 49 x 132 dots. The display can be expanded further using two chips. However, the ML9051G is not used in a multiple chip configuration when a line reversal drive is set. The ML9051G is made using a CMOS process. Because it has a built-in RAM, low power consumption is one of its features, and is therefore suitable for displays in battery-operated portable equipment. The ML9051G has 49 common signal outputs and 132 segment signal outputs and one chip can drive a display of up to 49 x 132 dots. FEATURES * Direct display of the RAM data using the bit map method Display RAM data "1" ... Dot is displayed Display RAM data "0" ... Dot is not displayed (during forward display) * Display RAM capacity 65 x 132 = 8580 bits * LCD Drive circuits 49 common outputs, 132 segment outputs * MPU interface: Can select an 8-bit parallel or serial interface * Built-in voltage multiplier circuit for the LCD drive power supply * Built-in LCD drive voltage adjustment circuit * Built-in LCD drive bias generator circuit * Can select frame reversal drive or line reversal drive by command * Built-in oscillator circuit (Internal RC oscillator/external clock input) * A variety of commands Read/write of display data, display ON/OFF, forward/reverse display, all dots ON/all dots OFF, set page address, set display start address, etc. * Power supply voltage Logic power supply: VDD-VSS = 3.7 V to 5.5 V Voltage multiplier reference voltage: VIN-VSS = 3.7 V to 5.5 V (2- to 4-time multiplier available) LCD Drive voltage: VBI-VSS = 6.0 to 18 V * Package: Gold bump chip (Bump hardness: Low, DV) * This device is not resistant to radiation and light. 1/74 PEDL9051G-01 OKI Semiconductor ML9051G BLOCK DIAGRAM SEG131 COMS0 Display timing generator circuit COMS COMS1 COM47 COMMON Drivers COM0 SEG0 VDD V1 V2 V3 V4 V5 VSS Common Output state selection circuit SEGMENT Drivers VS1- VS2- Page address circuit VC3+ Power supply circuit VC4+ VC5+ VC6+ VOUT VIN VR VRS IRS HPM Display data latch circuit FRS FR CL DOF M/S Display data RAM 65 x 132 Oscillator circuit Column address circuit Line address circuit I/O Buffer CLS TEST0 TEST1 Bus holder Command decoder Status MPU lnterface DB6(SCL) WR(R/W) DB7(SI) RD(E) P/ S CS2 RES CS1 DB4 DB3 DB1 C86 DB5 DB2 DB0 A0 2/74 PEDL9051G-01 OKI Semiconductor ML9051G ABSOLUTE MAXIMUM RATINGS VSS = 0 V Parameter Power supply voltage Bias voltage Voltage multiplier output voltage Voltage multiplier reference voltage Input voltage Storage temperature range Symbol VDD VBI VOUT Condition Tj = 25C Tj = 25C Tj = 25C 2-time multiplication VIN VI TSTG 3-time multiplication 4-time multiplication Tj = 25C Chip Rated value -0.3 to +7 -0.3 to +20 -0.3 to +20 -0.3 to +5.5 -0.3 to +5.5 -0.3 to +5.0 -0.3 to VDD+0.3 -55 to +125 V C All inputs -- V VIN Unit V V V Applicable pins VDD V1 to V5 VOUT Tj:Chip surface temperature RECOMMENDED OPERATING CONDITIONS VSS = 0 V Parameter Power supply voltage Bias voltage Voltage multiplier reference voltage Voltage multiplier output voltage Operating temperature range Symbol VDD VBI VIN Condition -- -- 2-time multiplication 3-time multiplication 4-time multiplication VOUT TJOP External input -- Rated value 3.7 to 5.5 6 to 18 3.7 to 5.5 3.7 to 5.5 3.7 to 4.5 6.0 to 18 -40 to +85 V C VOUT -- V VIN Unit V V Applicable pins VDD V1 to V5 Note 1: The electrical characteristics are influenced by COG trace resistance. This LSI always has to be evaluated before using. VOUT VIN VCC GND System (MPU) VDD VSS ML9051G V1 to V5 Note 2: Note 3: Note 4: The voltages VDD, V1 to V5, and VOUT are values taking VSS = 0 V as the reference. The highest bias potential is V1 and the lowest is VSS. Always maintain the relationship V1 V2 V3 V4 V5 VSS among these voltages. 3/74 PEDL9051G-01 OKI Semiconductor ML9051G Note 5: When using an external power supply, follow the procedure for power application. When applying external power to the VOUT pin only, apply VOUT after VDD. When applying external power to the V1 pin only, apply V1 after VDD. When applying external power to the V1 pin to V5 pin, apply V1 to V5 after VDD. Note that the above (Note 4) must be satisfied including transient state at power application. Note 6: When using an external power supply, follow the procedure for power removal described below. When external power is in use for the VOUT pin only, remove VOUT after VDD. When external power is in use for the V1 pin only, remove V1 after VDD. When external power is in use for the V1 pin to V5 pin, remove V1 to V5 after VDD. Note that the above (Note 4) must be satisfied including transient state at power removal. 4/74 PEDL9051G-01 OKI Semiconductor ML9051G ELECTRICAL CHARACTERISTICS DC Characteristics [VSS = 0 V, VDD = 3.7 to 5.5 V, Tj =-40 to +85C] Parameter "H" Input voltage "L" Input voltage "H" Input voltage "L" Input voltage Hysteresis width "H" output voltage "L" output voltage "H" Input current "L" Input current V1 output voltage temperature gradient V1 output voltage Voltage multiplier output voltage VOUT - V1 voltage LCD driver ON resistance Internal oscillation External input Symbol VIH VIL VIH VIL V VOH VOL IIH IIL V1TC V1 VDD = 5.0 V IOH = -0.5 mA IOL = 0.5 mA VI = VDD VI = 0 V Tj = 25C V1 = 12 V *6 3-time multiplication *7 4-time multiplication *8 *9 Condition Min 0.8 x VDD 0 0.8 x VDD 0 -- 0.8 x VDD -- -1.0 -3.0 -- 10.63 13.0 15.9 0.6 Typ -- -- -- -- 1.0 -- -- -- -- -0.05 10.85 -- -- -- Max VDD 0.2 x VDD VDD 0.2 x VDD -- -- 0.2 x VDD +1.0 +3.0 -- 11.07 -- -- -- V A %/C V V V V *3 *4 *5 V1 V1 VOUT VOUT VOUT, V1 SEG1 to 131, COMS0, COMS1, COM0 to 47 *10 V *2 Unit V Applicable pins *1 VOUT Vot1 RON IO = 50 A -- -- 10 k Oscillator frequency fOSC fEXT Tj = 25C 27 21 14 33 -- 17 39 47 20 kHz kHz kHz CL*10 *1: *2: *3: *4: *5: *6: *7: *8: A0, DB0 to DB5, DB7 (SI), CS1, CS2, CLS, FR, M/S, C86, P/S, DOF, IRS, HPM Pins RD (E), WR (R/W), RES, CL, DB6 (SCL) Pins DB0 to DB7, FR, FRS, DOF, CL Pins A0, RD (E), WR (R/W), CS1, CS2, CLS, M/S, C86, P/S, RES, IRS, HPM Pins Applicable to the pins DB0 to DB5, DB6 (SCL), DB7 (SI), CL, FR, DOF in the high impedance state. Tj = 25C, = 31, (1+Rb/Ra) = 4, VOUT = 13.5 V (External input), LCD drive output = no-load During high-power mode, VIN = 4.8 V, voltage multiplier capacitor C1 = 3.7 to 5.7 F, voltage multiplier output load current I = 500 A. Only a voltage multiplier circuit operates, not activating the voltage adjustment circuit and V/F circuit, by command "2C". During high-power mode, VIN = 4.5 V, voltage multiplier capacitor C1 = 3.7 to 5.7 F, voltage multiplier output load current I = 500 A. Only a voltage multiplier circuit operates, not activating the voltage adjustment circuit and V/F circuit, by command "2C". 5/74 PEDL9051G-01 OKI Semiconductor ML9051G *9: *10: During high-power mode, V1 load current I = 400 A. 8 V is externally input to VOUT. The voltage adjustment circuit and V/F circuit operate by command "2B". LCD output = no load See Table 1 for the relationship between the oscillator frequency and the frame frequency. Table 1. Relationship among the oscillator frequency (fOSC), display clock frequency (fLCDCK), and LCD frame frequency (fFR) Parameter ML9051G When the internal oscillator is used When the internal oscillator is not used Display clock frequency (fLCDCK) fOSC/8 External input (fLCDCK) LCD frame frequency (fFR) fOSC/(8 x 49) fLCDCK/196 6/74 PEDL9051G-01 OKI Semiconductor ML9051G * Operating current consumption value (1) During display operation, internal power supply OFF (The current flowing through VDD with V1 to V5 externally applied when an external power supply is used, not including the current for the LCD drive) [VSS = 0 V, Tj = 25C] Display mode All-white Checker pattern Symbol IDD IDD Condition VDD = 5 V, V1- VSS = 11 V, no load VDD = 3.7 V, V1- VSS = 8 V, no load VDD = 5 V, V1- VSS = 11 V, no load VDD = 3.7 V, V1- VSS = 8 V, no load Rated value Min -- -- -- -- Typ 25 15 25 15 Max 50 35 50 35 Unit A A (2) During display operation, internal power supply ON (Total of currents flowing through VDD and VIN) [VSS = 0 V, Tj = 25C] Display mode Symbol Condition Frame reversal, VDD, VIN = 5 V, 3-time voltage multiplication V1 - VSS= 11 V, no load Frame reversal, VDD, VIN = 3.7 V, 4-time voltage multiplication V1 - VSS= 8 V, no load 16-line reversal, VDD, VIN = 5 V, 3-time voltage multiplication V1 - VSS= 11 V, no load Frame reversal, VDD, VIN = 5 V, 3-time voltage multiplication V1 - VSS= 11 V, no load Checker pattern Frame reversal, VDD, VIN = 3.7 V, 4-time voltage multiplication V1 - VSS= 8 V, no load 16-line reversal, VDD, VIN = 5 V, 3-time voltage multiplication V1 - VSS= 11 V, no load Normal mode High-power mode Normal mode High-power mode Rated value Min -- -- -- -- Typ 225 515 255 605 Max 330 790 360 890 A Unit All-white IDDIN High-power mode -- 525 810 Normal mode High-power mode Normal mode High-power mode -- -- -- -- 295 585 325 675 430 860 515 A 1030 IDDIN High-power mode -- 595 875 * Power save mode current consumption [VSS = 0 V, Tj = 25C] Parameter Sleep mode Standby mode Symbol IDDS1 IDDS2 Condition VDD = 3.7 V VDD = 3.7 V Rated value Min -- -- Typ 0.3 7 Max 5 15 Unit A 7/74 PEDL9051G-01 OKI Semiconductor ML9051G Parallel Interface Timing Characteristics * System bus Write characteristics 1 (80-series MPU) VIH VIL tAW8 CS1 (CS2 = "H") tCYC8 WR tCCLW VIH VIL tDS8 DB0 to DB7 (Write) VIH VIL VIH VIL VIL VIH tCCHW tDH8 VIH VIH VIL tAH8 A0 * System bus Read characteristics 1 (80-series MPU) A0 VIH VIL tAW8 VIH VIL tAH8 CS1 (CS2 = "H") tCYC8 RD tCCLR VIH VIL VIL VIH tCCHR tACC8 DB0 to DB7 (Read) VOH VOL tOH8 VOH VOL VIH 8/74 PEDL9051G-01 OKI Semiconductor ML9051G [VDD = 4.5 to 5.5 V, Tj = -40 to +85C] Parameter Address hold time Address setup time System cycle time Control L pulse width (WR) Control L pulse width (RD) Control H pulse width (WR) Control H pulse width (RD) Data setup time Data hold time RD Access time Output disable time Symbol tAH8 tAW8 tCYC8 tCCLW tCCLR tCCHW tCCHR tDS8 tDH8 tACC8 tOH8 CL = 100 pF Condition Rated value Min 5 5 166 30 70 55 55 30 10 -- 5 Max -- -- -- -- -- -- -- -- -- 70 50 ns Unit [VDD = 3.7 to 4.5 V, Tj = -40 to +85C] Parameter Address hold time Address setup time System cycle time Control L pulse width (WR) Control L pulse width (RD) Control H pulse width (WR) Control H pulse width (RD) Data setup time Data hold time RD Access time Output disable time Symbol tAH8 tAW8 tCYC8 tCCLW tCCLR tCCHW tCCHR tDS8 tDH8 tACC8 tOH8 CL = 100 pF Condition Rated value Min 5 5 300 60 120 60 60 40 15 -- 10 Max -- -- -- -- -- -- -- -- -- 140 100 ns Unit Note 1: Note 2: Note 3: The input signal rise and fall times are specified as 15ns or less. When using the system cycle time for fast speed, the specified values are (tr + tf) (tCYC8 - tCCLW - tCCHW) or (tr + tf) (tCYC8 - tCCLR - tCCHR). All timings are specified taking the levels of 20% and 80% of VDD as the reference. The values of tCCLW and tCCLR are specified during the overlapping period of CS1 at "L" (CS2 = "H") and the "L" levels of WR and RD, respectively. 9/74 PEDL9051G-01 OKI Semiconductor ML9051G * System bus Write characteristics 2 (68-series MPU) VIH VIL VIH VIL tAH6 A0 R/W VIL tAW6 VIL CS1 (CS2 = "H") tCYC6 tEWHW E VIL VIH VIH VIL tEWLW tDS6 DB0 to DB7 (Write) VIH VIL tDH6 VIH VIL VIL * System bus Read characteristics 2 (68-series MPU) A0 VIH VIL VIH tAW6 VIH VIL tAH6 VIH R/W CS1 (CS2 = "H") tCYC6 tEWHR E VIL VIH VIH VIL tEWLR tACC6 DB0 to DB7 (Read) VOH VOL tOH6 VOH VOL VIL 10/74 PEDL9051G-01 OKI Semiconductor ML9051G [VDD = 4.5 to 5.5 V, Tj = -40 to +85C] Parameter Address hold time Address setup time System cycle time Data setup time Data hold time Access time Output disable time Enable H pulse width Enable L pulse width Read Write Read Write Symbol tAH6 tAW6 tCYC6 tDS6 tDH6 tACC6 tOH6 tEWHR tEWHW tEWLR tEWLW CL = 100 pF Condition Rated value Min 5 5 166 30 10 -- 10 70 30 60 60 Max -- -- -- -- -- 70 50 -- -- -- -- ns Unit [VDD = 3.7 to 4.5 V, Tj = -40 to +85C] Parameter Address hold time Address setup time System cycle time Data setup time Data hold time Access time Output disable time Enable H pulse width Enable L pulse width Read Write Read Write Symbol tAH6 tAW6 tCYC6 tDS6 tDH6 tACC6 tOH6 tEWHR tEWHW tEWLR tEWLW CL = 100 pF Condition Rated value Min 5 5 300 40 15 -- 10 120 60 60 60 Max -- -- -- -- -- 140 100 -- -- -- -- ns Unit Note 1: Note 2: Note 3: The input signal rise and fall times are specified as 15ns or less. When using the system cycle time for fast speed, the specified values are (tr + tf) (tCYC6 - tEWLW - tEWHW) or (tr + tf) (tCYC6 - tEWLR - tEWHR). All timings are specified taking the levels of 20% and 80% of VDD as the reference. The values of tEWLW and tEWLR are specified during the overlapping period of CS1 at "L" (CS2 = "H") and the "H" level of E. 11/74 PEDL9051G-01 OKI Semiconductor ML9051G Serial Interface Timing Characteristics * Serial interface tCSS CS1 (CS2 = "1") VIL tSAS A0 VIH VIL tSAH VIH VIL tSCYC SCL VIH VIL tf tSLW VIL tr tSDS SI VIH VIL tSDH VIH VIL VIH tSHW VIH VIL tCSH VIL [VDD = 4.5 to 5.5 V, Tj = -40 to +85C] Parameter Serial clock period SCL "H" Pulse width SCL "L" Pulse width Adress setup time Address hold time Data setup time Data hold time CS setup time CS hold time Symbol tSCYC tSHW tSLW tSAS tSAH tSDS tSDH tCSS tCSH Condition Rated value Min 200 75 75 50 100 50 50 100 100 Max -- -- -- -- -- -- -- -- -- ns Unit Note 1: Note 2: The input signal rise and fall times are specified as 15ns or less. All timings are specified taking the levels of 20% and 80% of VDD as the reference. 12/74 PEDL9051G-01 OKI Semiconductor ML9051G [VDD = 3.7 to 4.5 V, Tj = -40 to +85C] Parameter Serial clock period SCL "H" Pulse width SCL "L" Pulse width Address setup time Address hold time Data setup time Data hold time CS setup time CS hold time Symbol tSCYC tSHW tSLW tSAS tSAH tSDS tSDH tCSS tCSH Condition Rated value Min 250 100 100 150 150 100 100 150 150 Max -- -- -- -- -- -- -- -- -- ns Unit Note 1: Note 2: The input signal rise and fall times are specified as 15ns or less. All timings are specified taking the levels of 20% and 80% of VDD as the reference. * Display control output timing CL(OUT) VOH tDFR FR VIH VIL [VDD = 4.5 to 5.5 V, Tj = -40 to +85C] Parameter FR Delay time Symbol tDFR Condition CL = 50 pF Rated value Min -- Typ 10 Max 40 Unit ns [VDD = 3.7 to 4.5 V, Tj = -40 to +85C] Parameter FR Delay time Symbol tDFR Condition CL = 50 pF Rated value Min -- Typ 20 Max 80 Unit ns Note 1: Note 2: All timings are specified taking the levels of 20% and 80% of VDD as the reference. Valid only when the device operates in master mode. 13/74 PEDL9051G-01 OKI Semiconductor ML9051G * Reset input timing tf VIH RES tRW VIL tr VIH VIL tR Internal state Being reset Reset complete [VDD = 4.5 to 5.5 V, Tj = -40 to +85C] Parameter Reset time Reset "L" pulse width Symbol tR tRW Condition Rated value Min -- 0.5 Typ -- -- Max 0.5 -- Unit s [VDD = 3.7 to 4.5 V, Tj = -40 to +85C] Parameter Reset time Reset "L" pulse width Symbol tR tRW Condition Rated value Min -- 1 Typ -- -- Max 1 -- Unit s Note 1: Note 2: The input signal rise and fall times (tr, tf) are specified as 15 ns or less. All timings are specified taking the levels of 20% and 80% of VDD as the reference. 14/74 PEDL9051G-01 OKI Semiconductor ML9051G PIN DESCRIPTION Function Pin name Number of pins I/O Description These are 8-bit bi-directional data bus pins that can be connected to 8-bit standard MPU data bus pins. When a serial interface is selected (P/S = "L"): DB0 to DB7 DB7: Serial data input pin (SI) 8 I/O DB6: Serial clock input pin (SCL) In this case, DB0 to DB5 will be in the high impedance state. DB0 to DB7 will all be in the high impedance state when the chip select is in the inactive state. Fix the DB0 to DB5 pins at "H" or "L" level. Normally, the lowest bit of the MPU address bus is connected and used for distinguishing between data and commands. A0 = "H": Indicates that DB0 to DB7 is display data. A1 = "L": Indicates that DB0 to DB7 is control data. Initial setting is made by making RES = "L". The reset operation is made during the active level of the RES signal. These are the chip select signals. The Chip Select of the LSI becomes active when CS1 is "L" and also CS2 is "H" and allows the input/output of data or commands. The active level of this signal is "L" when connected to an 80-series MPU. This pin is connected to the RD signal of the 80-series MPU, and the data bus of the ML9051G goes into the output state when this signal is "L". 1 I The active level of this signal is "H" when connected to a 68-series MPU. This pin will be the Enable and clock input pin when connected to a 68-series MPU. When a serial interface is selected (P/S = "L"), fix this pin at "H" or "L" level. The active level of this signal is "L" when connected to an 80-series MPU. This pin is connected to the WR signal of the 80-series MPU. The data on the data bus is latched into the ML9051G at the rising edge of the WR signal. 1 I When connected to a 68-series MPU, this pin becomes the input pin for the Read/Write control signal. R/W = "H": Read, R/W = "L": Write When a serial interface is selected (P/S = "L"), fix this pin at "H" or "L" level. This is the pin for selecting the MPU interface type. A0 1 I RES CS1 1 I CS2 MPU Interface RD 2 I (E) WR (R/W) C86 1 I C86 = "H": 68-Series MPU interface. C86 = "L": 80-Series MPU interface. 15/74 PEDL9051G-01 OKI Semiconductor ML9051G Function Pin name Number of pins I/O Description This is the pin for selecting parallel data input or serial data input. P/S = "H": Parallel data input. P/S = "L": Serial data input. The pins of the LSI have the following functions depending on the state of P/S input. MPU Interface P/S 1 I P/S "H" "L" Data/command Data DB0 to DB7 SI (D7) Read/Write RD, WR Serial clock A0 A0 -- SCL(DB6) -- During serial data input, it is not possible to read the display data in the RAM This is the pin for selecting whether to enable or disable the internal oscillator circuit for the display clock. Oscillator circuit CLS 1 I CLS = "H": The internal oscillator circuit is enabled. CLS = "L": The internal oscillator circuit is disabled (External input). When CLS = "L", the display clock is input at the pin CL. This is the pin for selecting whether master operation or slave operation is made towards the ML9051G. During master operation, the synchronization with the LCD display system is achieved by inputting the timing signals necessary for LCD display. M/S = "H": Master operation M/S = "L": Slave operation Display timing generator circuit M/S 1 I The functions of the different circuits and pins will be as follows depending on the states of M/S and CLS signals. M/S "H" "L" CLS "H" "L" "H" "L" Oscillator circuit Enabled Disabled Disabled Disabled Power supply circuit Enabled Enabled Disabled Disabled CL Output Input Input Input FR Output Output Input Input FRS Output Output Output Output DOF Output Output Input Input 16/74 PEDL9051G-01 OKI Semiconductor ML9051G Function Pin name Number of pins I/O Description This is the display clock input/output pin. The function of this pin will be as follows depending on the states of M/S and CLS signals. M/S CLS "H" "L" "H" "L" CL Output Input Input Input CL 1 I/O "H" "L" Display timing generator circuit When the ML9051G is used in the master/slave mode, the corresponding CL pin has to be connected. This is the input/output pin for LCD display frame reversal signal. M/S = "H": Output FR 1 I/O M/S = "L": Input When the ML9051G is used in the master/slave mode, the corresponding FR pin has to be connected. This is the blanking control pin for the LCD display. M/S = "H": Output DOF 1 I/O M/S = "L": Input When the ML9051G is used in the master/slave mode, the corresponding DOF pin has to be connected. FRS 1 O This is the output pin for static drive. This pin is used in combination with the FR pin. This is the pin for selecting the resistor for adjusting the voltage V1. IRS = "H": The internal resistor is used. IRS = "L": The internal resistor is not used. The voltage V1 is adjusted using the external potential divider resistors connected to the pins VR. This pin is effective only in the master operation. This pin is tied to the "H" or the "L" level during slave operation. This is the power control pin for the LCD drive power supply circuit. HPM = "H": Normal mode IRS 1 I Power supply circuit HPM 1 I HPM = "L": High power mode This pin is effective only during master operation mode. This pin is tied to the "H" or the "L" level during slave operation. VDD VSS VIN 13 9 4 -- -- -- These pins are tied to the MPU power supply pin VCC. These are the 0 V pins connected to the system ground (GND). These are the reference power supply pins of the voltage multiplier circuit for driving the LCD. 17/74 PEDL9051G-01 OKI Semiconductor ML9051G Function Pin name VRS VOUT Number of pins 2 2 I/O -- I/O Description These are the test pins for the LCD power supply voltage adjustment circuit. Leave these pins open. These are the output pins during voltage multiplication. Connect a capacitor between these pins and VSS. These are the multiple level power supply pins for the LCD power supply. The voltages specified for the LCD cells are applied to these pins after resistor network voltage division or after impedance transformation using operational amplifiers. The voltages are specified taking VSS as the reference, and the following relationship should be maintained among them. V1 V2 V3 V4 V5 10 I/O V1 V2 V3 V4 V5 VSS Master operation: When the power supply is ON, the following voltages are applied to V2 to V5 from the built-in power supply circuit. The selection of voltages is determined by the LCD bias set command. ML9050E V2 V3 7/8 x V1 6/8 x V1 2/8 x V1 1/8 x V1 5/6 x V1 4/6 x V1 2/6 x V1 1/6 x V1 Power supply circuit V4 V5 Voltage adjustment pins. Voltages between V1 and VSS are applied using a resistance voltage divider. VR 2 I These pins are effective only when the internal resistors for voltage V1 adjustment are not used (IRS = "L"). Do not use these pins when the internal resistors for voltage V1 adjustment are used (IRS = "H"). VS1- 2 O These are the pins for connecting the negative side of the capacitors for voltage multiplication. Connect capacitors between these pins and VC3+, VC5+. VS2- 2 O These are the pins for connecting the negative side of the capacitors for voltage multiplication. Connect capacitors between these pins and VC4+, VC6+. VC3+ 2 O These are the pins for connecting the positive side of the capacitors for voltage multiplication. Connect capacitors between VS1- and these pins. VC4+ 2 O These are the pins for connecting the positive side of the capacitors for voltage multiplication. Connect capacitors between VS2- and these pins. 18/74 PEDL9051G-01 OKI Semiconductor ML9051G Function Pin name Number of pins 2 I/O Description These are the pins for connecting the positive side of the capacitors for voltage multiplication. Connect capacitors between VS1- and these pins. These are the pins for connecting the positive side of the capacitors for voltage multiplication. Connect capacitors between VS2- and these pins. These are the LCD segment drive outputs. One of the levels among V1, V3, V4, and VSS is selected depending on the combination of the display RAM content and the FR signal RAM Data FR H L H L -- Output voltage Forward display Reverse display V1 VSS V3 V4 VSS V3 V4 V1 VSS Power supply circuit VC5+ O VC6+ 2 O SEG0 to SEG131 132 O H H L L Power save LCD Drive output The output voltage is VSS when the Display OFF command is executed. These are the LCD common drive outputs. One of the levels among V1, V2, V5, and VSS is selected depending on the combination of the scan data and the FR signal. Scan data H COM0 to COM47 48 O H L L Power save FR H L H L -- Output voltage VSS V1 V2 V5 VSS The output voltage is VSS when the Display OFF command is executed. COMS0 COMS1 TEST0 TEST1 DUMMY These are the common output pins only for indicators. Both pins output the same signal. Leave these pins open when they are not used. The same signal is output in both master and slave operation modes. These are the pins for testing the IC chip. Leave these pins open during normal use. Leave this pin open. 2 O Test pin -- 1 1 72 I O -- 19/74 PEDL9051G-01 OKI Semiconductor ML9051G FUNCTIONAL DESCRIPTION MPU Interface MPU 80-Series 68-Series Read mode Pin RD = "L" Pin R/W = "H" Pin E = "H" Write mode Pin WR = "L" Pin R/W = "L" Pin E = "H" In the case of the 80-series MPU interface, a command is started by applying a low pulse to the RD pin or the WR pin. In the case of the 68-series MPU interface, a command is started by applying a high pulse to the E pin. * Selection of interface type The ML9051G carries out data transfer using either the 8-bit bi-directional data bus (DB0 to DB7) or the serial data input line (SI). Either the 8-bit parallel data input or serial data input can be selected as shown in Table 2 by setting the P/S pin to the "H" or the "L" level. Table 2 Selection of interface type (parallel/serial) P/S H: Parallel input L: Serial input CS1 CS1 CS1 CS2 CS2 CS2 A0 A0 A0 RD RD WR WR C86 C86 -- D7 D7 SI D6 D6 SCL DB0 to DB5 DB0 to DB5 -- -- -- A hyphen (--) indicates that the pin can be tied to the "H" or the "L" level. * Parallel interface When the parallel interface is selected, (P/S = "H"), it is possible to connect this LSI directly to the MPU bus of either an 80-series MPU or a 68-series MPU as shown in Table 3. depending on whether the pin C86 is set to "H" or "L". Table 3 Selection of MPU during parallel interface (80-/68-series) C86 H: 68-Series MPU bus L: 80-Series MPU bus CS1 CS1 CS1 CS2 CS2 CS2 A0 A0 A0 RD WR DB0 to DB7 DB0 to DB7 DB0 to DB7 E RD R/W WR The data bus signals are identified as shown in Table 4 below depending on the combination of the signals A0, RD (E), and WR (R/W) of Table 3. Table 4 Identification of data bus signals during parallel interface Common A0 Display data read Display data write Status read Control data write (command) 1 1 0 0 68-Series R/W 1 0 1 0 RD 80-Series WR 0 1 0 1 1 0 1 0 20/74 PEDL9051G-01 OKI Semiconductor ML9051G Serial Interface When the serial interface is selected (P/S = "L"), the serial data input (SI) and the serial clock input (SCL) can be accepted if the chip is in the active state (CS1 = "L" and CS2 = "H"). The serial interface consists of an 8-bit shift register and a 3-bit counter. The serial data is read in from the serial data input pin in the sequence DB7, DB6, ... , DB0 at the rising edge of the serial clock input, and is converted into parallel data at the rising edge of the 8th serial clock pulse and processed further. The identification of whether the serial data is display data or command is judged based on the A0 input, and the data is treated as display data when A0 is "H" and as command when A0 is "L". The A0 input is read in and identified at the rising edge of the (8 x n) th serial clock pulse after the chip has become active. Fig. 1 shows the signal chart of the serial interface. (When the chip is not active, the shift register and the counter are reset to their initial states. No data read out is possible in the case of the serial interface. It is necessary to take sufficient care about wiring termination reflection and external noise in the case of the SCL signal. We recommend verification of operation in an actual unit.) CS1 CS2 SI SCL A0 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 DB7 DB6 DB5 DB4 DB3 DB2 1 2 3 4 5 6 7 8 9 10 11 12 13 14 Fig. 1 Signal chart during serial interface * Chip select The ML9051G has the two chip select pins CS1 and CS2, and the MPU interface or the serial interface is enabled only when CS1 = "L" and CS2 = "H". When the chip select signals are in the inactive state, the DB0 to DB7 lines will be in the high impedance state and the inputs A0, RD, and WR will not be effective. When the serial interface has been selected, the shift register and the counter are reset when the chip select signals are in the inactive state. * Accessing the display data RAM and the internal registers Accessing the ML9051G from the MPU side requires merely that the cycle time (tCYC) be satisfied, and high speed data transfer without requiring any wait time is possible. Also, during the data transfer with the MPU, the ML9051G carries out a type of pipeline processing between LSIs via a bus holder associated with the internal data bus. For example, when the MPU writes data in the display data RAM, the data is temporarily stored in the bus holder, and is then written into the display data RAM before the next data read cycle. Further, when the MPU reads out data in the display data RAM, first a dummy data read cycle is carried out to temporarily store the data in the bus holder which is then placed on the system bus and is read out during the next read cycle. There is a restriction on the read sequence of the display data RAM, which is that the read instruction immediately after setting the address does not read out the data of that address, but that data is output as the data of the address specified during the second data read sequence, and hence care should be taken about this during reading. Therefore, always one dummy read is necessary immediately after setting the address or after a write cycle: (The status read cannot use dummy read cycles.) This relationship is shown in Figs 2(a) and 2(b). 21/74 PEDL9051G-01 OKI Semiconductor ML9051G * Data write WR MPU DATA Internal timing Dn Latch Dn Dn + 1 Dn + 1 Dn + 2 Dn + 2 Dn + 3 Dn + 3 BUS Holder Write Signal Fig. 2(a) Write sequence of display data RAM * Data read WR MPU RD DATA Address Preset Internal timing N unknown Dn Dn + 1 Read Signal Column Address BUS Holder Address Set N Preset N unknown Data Read (Dummy) Increment N + 1 Dn Data Read Dn N+2 Dn + 1 Dn + 2 Data Read Dn + 1 Fig. 2(b) Read sequence of display data RAM Dn = Data N = Address data * Busy flag The busy flag being "1" indicates that the ML9051G is carrying out reset operations, and hence no instruction other than a status read instruction is accepted during this period. The busy flag is output at pin DB7 when a status read instruction is executed. 22/74 PEDL9051G-01 OKI Semiconductor ML9051G Display Data RAM * Display data RAM This is the RAM storing the dot data for display and has an organization of 65 (8 pages x 8 bits +1) x 132 bits. It is possible to access any required bit by specifying the page address and the column address. Since the display data DB7 to DB0 from the MPU corresponds to the LCD display in the direction of the common lines as shown in Fig. 3, there are fewer restrictions during display data transfer when the ML9051G is used in a multiple chip configuration, thereby making it easily possible to realize a display with a high degree of freedom. Also, since the display data RAM read/write from the MPU side is carried out via an I/O buffer, it is done independent of the signal read operation for the LCD drive. Consequently, the display is not affected by flickering, etc., even when the display data RAM is accessed asynchronously during the LCD display operation. DB0 DB1 DB2 DB3 DB4 0 1 0 0 1 1 0 0 1 0 1 0 0 1 0 1 0 0 1 0 ... ... ... ... ... 0 0 0 0 0 COM0 COM1 COM2 COM3 COM4 LCD Display ... ... ... ... ... Display data RAM Fig. 3 Relationship between display data RAM and LCD display * Page address circuit The page address of the display data RAM is specified using the page address set command as shown in Fig. 4. Specify the page address again when accessing after changing the page. The page address 8 (DB3, DB2, DB1, DB0 1, 0, 0, 0) is the RAM area dedicated to the indicator, and only the display data DB0 is valid in this page. * Column address circuit The column address of the display data RAM is specified using the column address set command as shown in Fig. 4. Since the specified column address is incremented (by +1) every time a display data read/write command is issued, the MPU can access the display data continuously. Further, the incrementing of the column address is stopped at the column address of 83(H). Since the column address and the page address are independent of each other, it is necessary, for example, to specify separately the new page address and the new column address when changing from column 83(H) of page 0 to column 00(H) of page 1. Also, as is shown in Table 5, it is possible to reverse the correspondence relationship between the display data RAM column address and the segment output using the ADC command (the segment driver direction select command). This reduces the IC placement restrictions at the time of assembling LCD modules. Table 5 Correspondence relationship between the display data RAM column address and the segment output ADC DB0 = "0" DB0 = "1" SEGMENT Output SEG0 0(H) 83(H) SEG131 Column Address Column Address 83(H) 0(H) 23/74 PEDL9051G-01 OKI Semiconductor ML9051G * Line address circuit The line address circuit is used for specifying the line address corresponding to the common output when displaying the contents of the display data RAM as is shown in Fig. 4. Normally, the topmost line in the display is specified using the display start line address set command (COM0 output in the forward display state of the common output, and COM47 output in the reverse display state). The display area is 48 lines in the direction of increasing line address from the specified display start line address. When the indicator-dedicated common output pin (COMS) is selected, data in Line Address 40 H = page 8 and bit 0 is displayed irrespective of the display start line address. COMS selection is 49th in order. It is possible to carry out screen scrolling by dynamically changing the line address using the display start line address set command. * Display data latch circuit The display data latch circuit is a latch for temporarily storing the data from the display data RAM before being output to the LCD drive circuits. Since the commands for selecting forward/reverse display and turning the display ON/OFF control the data in this latch, the data in the display data RAM will not be changed. Oscillator Circuit This is an RC oscillator that generates the display clock. The oscillator circuit is effective only when M/S = "H" and also CLS = "H". The oscillations will be stopped when CLS = "L", and the display clock has to be input to the CL pin. 24/74 PEDL9051G-01 OKI Semiconductor ML9051G Page Address Data Line Address When the common output state is normal display COM Output 0000 0001 0010 0011 0100 0101 0110 0111 1000 DB0 DB1 DB2 DB3 DB4 DB5 DB6 DB7 DB0 DB1 DB2 DB3 DB4 DB5 DB6 DB7 DB0 DB1 DB2 DB3 DB4 DB5 DB6 DB7 DB0 DB1 DB2 DB3 DB4 DB5 DB6 DB7 DB0 DB1 DB2 DB3 DB4 DB5 DB6 DB7 DB0 DB1 DB2 DB3 DB4 DB5 DB6 DB7 DB0 DB1 DB2 DB3 DB4 DB5 DB6 DB7 DB0 DB1 DB2 DB3 DB4 DB5 DB6 DB7 DB0 83(H) 00(H) 82(H) 01(H) 81(H) 02(H) 80(H) 03(H) 7F(H) 04(H) 7E(H) 05(H) 7D(H) 06(H) 7C(H) 07(H) Page0 Page1 Page2 Page3 Page4 Page5 Page6 Page7 Page8 7F(H) 80(H) 81(H) 82(H) 83(H) 00H 01H 02H 03H 04H 05H 06H 07H 08H 09H 0AH 0BH 0CH 0DH 0EH 0FH 10H 11H 12H 13H 14H 15H 16H 17H 18H 19H 1AH 1BH 1CH 1DH 1EH 1FH (Start) 20H 21H 22H 23H 24H 25H 26H 27H 28H 29H 2AH 2BH 2CH 2DH 2EH 2FH 30H 31H 32H 33H 34H 35H 36H 37H 38H 39H 3AH 3BH 3CH 3DH 3EH 3FH 40H 48 Lines 1 0 DB0 DB0 ADC Column Address COM0 COM1 COM2 COM3 COM4 COM5 COM6 COM7 COM8 COM9 COM10 COM11 COM12 COM13 COM14 COM15 COM16 COM17 COM18 COM19 COM20 COM21 COM22 COM23 COM24 COM25 COM26 COM27 COM28 COM29 COM30 COM31 COM32 COM33 COM34 COM35 COM36 COM37 COM38 COM39 COM40 COM41 COM42 COM43 COM44 COM45 COM46 COM47 COMS The 40(H) is displayed irrespective of the display start line address. SEG127 04(H) SEG128 03(H) SEG129 02(H) SEG130 01(H) SEG131 00(H) SEG0 SEG1 SEG2 SEG3 SEG4 SEG5 SEG6 SEG7 Fig. 4 Display data RAM address map LCD Output 25/74 PEDL9051G-01 OKI Semiconductor ML9051G Display Timing Generator Circuit This circuit generates the timing signals for the line address circuit and the display data latch circuit from the display clock. The display data is latched in the display data latch circuit and is output to the segment drive output pins in synchronization with the display clock. This circuit generates the timing signals for the line address circuit and the display data latch circuit from the display clock. The display data is latched in the display data latch circuit and is output to the segment drive output pins in synchronization with the display clock. The read out of the display data to the LCD drive circuits is completely independent of the display data RAM access from the MPU. As a result, there is no bad influence such as flickering on the display even when the display data RAM is accessed asynchronously during the LCD display. Also, the internal common timing and LCD frame reversal (FR) signals are generated by this circuit from the display clock. The drive waveforms of the frame reversal drive method shown in Fig. 5(a) for the LCD drive circuits are generated by this circuit. The drive waveforms of the line reversal drive method shown in Fig. 5(b) are also generated by the command. 48 49 1 2 3 4 5 6 44 45 46 47 48 49 1 2 3 4 5 6 LCDCK (display clock) FR V1 V2 COM0 V5 VSS V1 V2 COM1 V5 VSS RAM DATA V1 V3 V4 VSS SEGn Fig. 5(a) Waveforms in the frame reversal drive method 26/74 PEDL9051G-01 OKI Semiconductor ML9051G 48 49 1 2 3 4 5 6 44 45 46 47 48 49 1 2 3 4 5 6 LCDCK (display clock) FR V1 V2 COM0 V5 VSS V1 V2 COM1 V5 VSS RAM DATA V1 V3 V4 VSS SEGn Fig. 5(b) Waveforms in the line reversal drive method When the ML9051G is used in a multiple chip configuration, it is necessary to supply the slave side display timing signals (FR, CL, and DOF) from the master side. However, when the line reversal drive is set, the ML9051G is not used in a multiple chip configuration. The statuses of the signals FR, CL, and DOF are shown in Table 6. Table 6 Display timing signals in master mode and slave mode Operating mode Master mode (M/S = "H") Slave mode (M/S = "L") Internal oscillator circuit enabled (CLS = H) Internal oscillator circuit disabled (CLS = L) Internal oscillator circuit disabled (CLS = H) Internal oscillator circuit disabled (CLS = L) FR Output Output Input Input CL Output Input Input Input DOF Output Output Input Input Note: During master mode, the oscillator circuit operates from the time the power is applied. The oscillator circuit can be stopped only in the sleep state. 27/74 PEDL9051G-01 OKI Semiconductor ML9051G Common Output State Selection Circuit (see Table 7) Since the common output scanning directions can be set using the common output state selection command in the ML9051G, it is possible to reduce the IC placement restrictions at the time of assembling LCD modules. Table 7 Common output state settings State Forward Display Reverse Display Common Scanning direction COM0 COM47 COM47 COM0 LCD Drive Circuit This LSI incorporates 181 sets of multiplexers for the ML9051G, that generate 4-level outputs for driving the LCD. These output the LCD drive voltage in accordance with the combination of the display data, common scanning signals, and the FR signal. Fig. 6 shows examples of the segment and common output waveforms in the frame reversal drive method. Static Indicator Circuit The FR pin is connected to one side of the LCD drive electrode of the static indicator and the FRS pin is connected to the other side. The static indicator display is controlled by a command only independently of other display control commands. The electrode of the static indicator should has a wiring pattern that is distant from the dynamic drive electrode. If the wiring pattern is placed too near to the dynamic drive electrode, the LCD and electrode may be degraded. 28/74 PEDL9051G-01 OKI Semiconductor SEG0 SEG1 SEG2 SEG3 SEG4 ML9051G COM0 COM1 COM2 COM3 COM4 COM5 COM6 COM7 COM8 COM9 CO M10 CO M11 CO M12 CO M13 CO M14 CO M15 FR V DD V SS V1 V2 V3 V4 V5 V SS V1 V2 V3 V4 V5 V SS V1 V2 V3 V4 V5 V SS V1 V2 V3 V4 V5 V SS V1 V2 V3 V4 V5 V SS V1 V2 V3 V4 V5 V SS V1 V2 V3 V4 V5 0V -V 5 -V 4 -V 3 -V 2 -V 1 V1 V2 V3 V4 V5 0V -V 5 -V 4 -V 3 -V 2 -V 1 COM0 COM1 COM2 SEG0 SEG1 SEG2 C O M 0 -S E G 0 C O M 0 -S E G 1 Fig. 6 Output waveforms in the frame reversal drive method (FR waveform/common waveform/segment waveform/voltage difference between common and segment) 29/74 PEDL9051G-01 OKI Semiconductor ML9051G Power Supply Circuit This is the low power consumption type power supply circuit for generating the voltages necessary for driving LCD devices, and consists of voltage multiplier circuits, voltage adjustment circuits, and voltage follower circuits. In the power supply circuit, it is possible to control the ON/OFF of each of the circuits of the voltage multiplier, voltage adjustment circuits, and voltage follower circuits using the power control set command. As a result, it is also possible to use parts of the functions of both the external power supply and the internal power supply. Table 8 shows the functions controlled by the 3-bit data of the power control set command and Table 9 shows a sample combination. Table 8 Details of functions controlled by the bits of the power control set command Control bit DB2 DB1 DB0 Function controlled by the bit Voltage multiplier circuit control bit Voltage adjustment circuit (V1 voltage adjustment circuit) control bit Voltage follower circuit (V/F circuit) control bit Table 9 Sample combination for reference Circuit State used Only the internal power supply is used Only V adjustment and V/F circuits are used Only V/F circuits are used Only the external power supply is used DB2 DB1 DB0 Voltage multiplier V Adjustment V/F External voltage input VIN Voltage multiplier pins *1 Used OPEN OPEN OPEN 1 0 0 0 1 1 0 0 1 1 1 0 x x x x x x VOUT V1 V1 to V5 *1: The voltage multiplier pins are the pins VS1-, VS2-, VC3+, VC4+, VC5+, and VC6+. If combinations other than the above are used, normal operation is not guaranteed. 30/74 PEDL9051G-01 OKI Semiconductor ML9051G * Voltage multiplier circuits The connections for 2- to 4-time voltage multiplier circuits are shown below. VIN VSS + + OPEN VOUT VC6+ VC4+ + + VIN VSS VOUT VC6+ VC4+ + + + VIN VSS VOUT VC6+ VC4+ VS2- VC5+ OPEN VC3+ + OPEN VS2- VC5+ VC3+ + VS2- VC5+ VC3+ VS1- 2-time voltage multiplier circuit VS1- 3-time voltage multiplier circuit VS1- 4-time voltage multiplier circuit Fig. 7 Connection examples for voltage multiplier circuits 31/74 PEDL9051G-01 OKI Semiconductor ML9051G The voltage relationships in voltage multiplication are shown in Fig. 8. VOUT = 3 x VIN = 15.0 V VOUT = 4 x VIN = 18 V *1 VIN VSS = 5.0 V =0V *1 VIN = 4.5 V VSS = 0 V Voltage relationship in 4-time multiplication Voltage relationship in 3-time multiplication Fig. 8 Voltage relationships in voltage multiplication *1: The voltage range of VIN should be set so that the voltage at the pin VOUT does not exceed the voltage multiplier output voltage operating range. * Voltage adjustment circuit The voltage multiplier output VOUT produces the LCD drive voltage V1 via the voltage adjustment circuit. Since the ML9051G incorporates a high accuracy constant voltage generator, a 64-level electronic potentiometer function, and also resistors for voltage V1 adjustment, it is possible to build a high accuracy voltage adjustment circuit with very few components. In addition, the ML9051G is available with the temperature gradients of a VREG - about -0.05%/C. (a) When the internal resistors for voltage V1 adjustment are used It is possible to control the LCD power supply voltage V1 and adjust the intensity of LCD display using commands and without needing any external resistors, if the internal voltage V1 adjustment resistors and the electronic potentiometer function are used. The voltage V1 can be obtained by the following equation A-1 in the range of V1 VEV (Constant voltage supply + electronic potentiometer) + V1 - VR Internal Ra Internal Rb Fig. 9 V1 voltage adjustment circuit (equivalent circuit) 32/74 PEDL9051G-01 OKI Semiconductor ML9051G VREG is a constant voltage generated inside the IC and VRS pin output voltage. Here, is the electronic potentiometer function which allows one level among 64 levels to be selected by merely setting the data in the 6-bit electronic potentiometer register. The values of set by the electronic potentiometer register are shown in Table 10. Table 10 Relationship between electronic potentiometer register and 63 62 61 ... DB5 0 0 0 ... DB4 0 0 0 ... DB3 0 0 0 ... DB2 0 0 0 ... DB1 0 0 1 ... DB0 0 1 0 ... 1 0 1 1 1 1 1 1 1 1 1 1 0 1 Rb/Ra is the voltage V1 adjustment internal resistor ratio and can be adjusted to one of 8 levels by the voltage V1 adjustment internal resistor ratio set command. The reference values of the ratio (1 + Rb/Ra) according to the 3-bit data set in the voltage V1 adjustment internal resistor ratio setting register are listed in Table 11. Table 11 Voltage V1 adjustment internal resistor ratio setting register values and the ratio (1+Rb/Ra) (Nominal) Register DB2 0 0 0 0 1 1 1 DB1 0 0 1 1 0 0 1 DB0 0 1 0 1 0 1 0 (1 + Rb/Ra) 3.0 3.5 4.0 4.5 5.0 5.5 6.0 Note: Use V1 gain in the range from 3 to 6 times. Because this LSI has temperature gradient, V1 voltage rises at lower temperatures. When using V1 gain of 6 times, adjust the built-in electronic potentiometer so that V1 voltage does not exceed 18 V. When V1 is set using the built-in resistance ratio, the accuracies are shown in Table 12. Table 12 Relation between V1 Output Voltage Accuracy and V1 Gain Using Built-in Resistor Parameter V1 output voltage accuracy V1 maximum output voltage V1 gain 3 times 3.5 times 4 times 4.5 times 5 times 5.5 times 6 times Unit % V 2 9 2 10.5 2 12 2 13.5 2 15 +2, -3 16.5 +2, -4 18 Note: The V1 maximum output voltages in Table 12 are nominal values when Tj = 25C, and electronic potentiometer = 0. 33/74 PEDL9051G-01 OKI Semiconductor ML9051G (b) When external resistors are used (voltage V1 adjustment internal resistors are not used) It is also possible to set the LCD drive power supply voltage V1 without using the internal resistors for voltage V1 adjustment but connecting external resistors (Ra' and Rb') between VSS & VR and between VR & V1. Even in this case, it is possible to control the LCD power supply voltage V1 and adjust the intensity of LCD display using commands if the electronic potentiometer function is used. The voltage V1 can be obtained by the following equation B-1 in the range of V1 Fig. 10 V1 voltage adjustment circuit (equivalent circuit) Setting example: Setting V1 = 7 V at Tj = 25C When the electronic potentiometer register value is set to the middle value of (DB5, DB4, DB3, DB2, DB1, DB0) = (1, 0, 0, 0, 0, 0), the value of will be 31 and that of VREG will be 3.0 V, and hence the equation B-1 becomes as follows: V1 = (1 + (Rb'/Ra')) * (1 - (/324)) * VREG 7 = (1 + (Rb'/Ra')) * (1 - (31/324)) * 3.0 (Eqn. B-2) Further, if the current flowing through Ra' and Rb' is set as 5 A, the value of Ra' + Rb' will be - Ra' + Rb' = 1.4 M (Eqn. B-3) and hence, Rb'/Ra' = 1.58, Ra' = 543 k, Rb' = 857 k. In this case, the variability range of voltage V1 using the electronic potentiometer function will be as given in Table 13. Table 13 Example 1 of V1 variable-voltage range using electronic potentiometer function V1 Variable-voltage range Min 6.24 ( = 63) Typ 7.0 ( = 31) Max 7.74 ( = 0) Unit [V] 34/74 PEDL9051G-01 OKI Semiconductor ML9051G (c) When external resistors are used (voltage V1 adjustment internal resistors are not used) and a variable resistor is also used It is possible to set the LCD drive power supply voltage V1 using fine adjustment of Ra' and Rb' by adding a variable resistor to the case of using external resistors in the above case. Even in this case, it is possible to control the LCD power supply voltage V1 and adjust the intensity of LCD display using commands if the electronic potentiometer function is used. The voltage V1 can be obtained by the following equation C-1 in the range of V1 VSS Fig. 11 V1 voltage adjustment circuit (equivalent circuit) Setting example: Setting V1 in the range 5 V to 9 V using R2 at Tj = 25C . When the electronic potentiometer register value is set to (DB5, DB4, DB3, DB2, DB1, DB0) = (1, 0, 0, 0, 0, 0), the value of will be 31 and that of VREG will be 3.0 V, and hence in order to make V1 = 9 V when R2 = 0, the equation C-1 becomes as follows: 9 = (1 + (R3 + R2)/R1) * (1 - (31/324)) * (3.0) (Eqn. C-2) In order to make V1 = 5 V when R2 = R2, 5 = (1 + R3/(R1+R2)) * (1 - (31/324)) * (3.0) (Eqn. C-3) Further, if the current flowing between VSS and V1 is set as 5 A, the value of R1 + R2 + R3 becomesR1 + R2 + R3 = 1.8 M (Eqn. C-4) and hence, R1 = 542 k, R2 = 436 k, R3 = 822 k. In this case, the variability range of voltage V1 using the electronic potentiometer function and the increment size will be as given in Table 13. Table 14 Example 2 of V1 variable-voltage range using electronic potentiometer function and variable resistor V1 Variable-voltage range Min 4.45 ( = 63) Typ 7.0 ( = 31) Max 9.96 ( = 0) Unit [V] 35/74 PEDL9051G-01 OKI Semiconductor ML9051G In Figures 10 and 11, the voltage VEV is obtained by the following equation by setting the electronic potentiometer between 0 and 63. VEV = (1 - (/324)) * VREG = 0: VEV = (1 - (0/324)) * 3.0 V = 3.0 V = 31: VEV = (1 - (31/324)) * 3.0 V = 2.712 V = 63: VEV = (1 - (63/324)) * 3.0 V = 2.416 V The increment size of the electronic potentiometer at VEV when VREG = 3.0 is : = 3.0 - 2.416 63 = 9.27 mV (Nominal) When VREG = 3.069 V, = 0 : VEV = 3.069 V, = 63 : VEV = 2.472 V The increment size is : = 3.069 V - 2.472 V 63 = 9.476 mV When VREG = 2.931 V, = 0 : VEV = 2.931 V, = 63 : VEV = 2.361 V The increment size is : = 2.931 V - 2.361 V 63 = 9.047 mV 36/74 PEDL9051G-01 OKI Semiconductor ML9051G * When using the voltage V1 adjustment internal resistors or the electronic potentiometer function, it is necessary to set at least the voltage adjustment circuit and the voltage follower circuits both in the operating state using the power control setting command. Also, when the voltage multiplier circuit is OFF, it is necessary to supply a voltage externally to the VOUT pin. * The pin VR is effective only when the voltage V1 adjustment internal resistors are not used (pin IRS = "L"). Leave this pin open when the voltage V1 adjustment internal resistors are being used (pin IRS = "H"). * Since the input impedance of the pin VR is high, it is necessary to take noise countermeasures such as using short wiring length or a shielded wire . * The supply current increases in proportion to the panel capacitance. When power consumption increases, the VOUT level may fall. The voltage (VOUT - V1) should be more than 3 V. * LCD Drive voltage generator circuits The voltage V1 is divided using resistors inside the IC to generate the voltages V2, V3, V4, and V5 that are necessary for driving the LCD. In addition, these voltages V2, V3, V4, and V5 are impedance transformed using voltage follower circuits and fed to the LCD drive circuits. The bias ratio of 1/8 or 1/6 can be selected using the LCD bias setting command. * High power mode The power supply circuit incorporated in the ML9051G has an extremely low power consumption. [Normal mode: HPM = "H"]. Hence, in the case of an LCD device or panel with a large load, the display quality may become poorer. In such a case, setting the HPM pin to "L"s (high power mode) can improve the quality of display. It is recommended to verify the display using an actual unit in order to decide whether or not to use this mode. Further, if the degree of display quality improvement is still not sufficient even after setting the high power mode, it is necessary to supply the LCD drive power supply from an external source. * At built-in power-on, and transition from power save state to display mode After built-in power-on, at the command "2F(H)" input, or on transition from power save state to display mode, the display does not operate for a maximum period of 300 ms until the built-in power is stabilized. This period of no display is not influenced by display ON/OFF command. Despite input of display ON command during this period, the display does not operate for this period. However, the command is valid. After the wait time is finished, the display operates. (During this period of no display, all commands are acceptable.) * Command sequence for shutting off the internal power supply When shutting off the internal power supply, it is recommended to use the procedure given in Fig. 12 of switching OFF the power after putting the LSI in the power save state using the following command sequence. Procedure Step1 Step2 End Description (Command, status) Display OFF Display all ON Internal power supply OFF Commands DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 1 0 1 0 1 1 1 0 1 0 1 0 0 1 0 1 Power save commands (multiple commands) Fig. 12 Command sequence for shutting off the internal power supply 37/74 PEDL9051G-01 OKI Semiconductor ML9051G * Application circuits (Two V1 pins are described in the following examples for explanation, but they are the same.) (1) When the voltage multiplier circuit, voltage adjustment circuit, and V/F circuits are all used When using the internal voltage V1 adjustment resistors VIN = VDD 3-time voltage multiplication (2) When the voltage multiplier circuit, voltage adjustment circuit, and V/F circuits are all used When not using the internal voltage V1 adjustment resistors VIN = VDD 3-time voltage multiplication VDD VDD IRS VIN VC6+ VC4+ VS2- M/S IRS VIN VC6+ VC4+ VS2- M/S + C1 + C1 + C1 OPEN VC5+ VC3+ VS1- V1 VR VSS VOUT V1 V2 V3 V4 V5 + C1 OPEN VC5+ VC3+ VS1- V1 VR VSS VOUT V1 V2 V3 V4 V5 OPEN VSS R1 VSS R2 R3 C1 C1 C2 C2 C2 C2 C1: *1 C2: *2 C1 C1 C2 C2 C2 C2 + + + + + + Rall=R1+R2+R3 Rall: *3 C1:*1 C2: *2 + + + + + + (3) When only the voltage adjustment circuit and V/F circuits (4) When only the voltage adjustment circuit and V/F circuits are used are used When not using the internal voltage V1 adjustment resistors When using the internal voltage V1 adjustment resistors VDD IRS VIN VC6+ VC4+ VS2- VC5+ VC3+ VS1- V1 VR VSS VOUT V1 V2 V3 V4 V5 M/S VDD IRS VIN VC6+ VC4+ VS2- VC5+ VC3+ VS1- V1 VR VSS VOUT M/S OPEN OPEN OPEN OPEN OPEN OPEN R1 R2 R3 VSS External power supply OPEN OPEN OPEN OPEN OPEN OPEN OPEN VSS External power supply Rall=R1+R2+R3 Rall: *3 C1: *1 C2: *2 C1 C2 C2 C2 C2 + + + + + C1: *1 C2: *2 C1 C2 C2 C2 C2 + + + + + V1 V2 V3 V4 V5 38/74 PEDL9051G-01 OKI Semiconductor ML9051G (5) When only the V/F circuits are used (6) When not using the internal power supply VDD VDD OPEN OPEN OPEN OPEN OPEN OPEN OPEN VSS IRS VIN VC6+ VC4+ VS2- VC5+ VC3+ VS1- V1 VR VSS VOUT V1 V2 V3 V4 V5 M/S OPEN OPEN OPEN OPEN OPEN OPEN OPEN VSS IRS VIN VC6+ VC4+ VS2- VC5+ VC3+ VS1- V1 VR VSS VOUT V1 V2 V3 V4 V5 M/S External power supply OPEN C2 C2 C2 C2 + + + + OPEN External power supply C2: *2 Note: When trace resistance external to COG-mounted chip does not exist, when C1 (*1) = 0.9 F to 5.7 F, C2 (*2) = 0.42 F to 1.2 F, use in the range Rall (*3) = 1 M to 5 M. when C1 (*1) = 3.7 F to 5.7 F, C2 (*2) = 0.42 F to 1.2 F, use in the range Rall (*3) = 500 k to 5 M. Make sure that voltage multiplier output voltage, and V1 output voltage have enough margin before using this LSI. * Initial setting Note: If electric charge remains in smoothing capacitor connected between the LCD driver voltage output pins (V1 to V5) and the VSS pin, a malfunction might occur: the display screen gets dark for an instant when powered on. To avoid a malfunction at power-on, it is recommended to follow the flowchart in the "EXAMPLES OF SETTINGS FOR THE INSTRUCTIONS" section in page 54. 39/74 PEDL9051G-01 OKI Semiconductor ML9051G LIST OF OPERATION No 1 2 3 Operation Display OFF Display ON Display start line set Page address set Column address set (upper bits) Column address set (lower bits) Status read Display data write Display data read Forward 8 ADC select Reverse Forward 9 Display Reverse OFF(Normal DBn 76543210 10101110 10101111 0 1 Address 1 0 1 1 Address 0 0 0 1 Address (upper) 0 0 0 0 Address (lower) Status * * * * Write data Read data 10100000 10100001 10100110 10100111 10100100 10100101 10100010 A0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RD 1 1 WR 0 0 Comment LCD Display: OFF when DB0 = 0 ON when DB0 = 1 The display starting line address in the display RAM is set. The page address in the display RAM is set. The upper 4 bits of the column address in the display RAM is set. The lower 4 bits of the column address in the display RAM is set. The status information is read out from the upper 4 bits. Writes data to the display data RAM. Reads data from the display data RAM. Correspondence to the segment output for the display data RAM address Forward when DB0 = 0 Reverse when DB0 = 1 Forward or reverse LCD display mode Forward when DB0 = 0 Reverse when DB0 = 1 LCD Normal display when DB0 = 0 All-on display when DB0 = 1 Sets the LCD drive voltage bias ratio. 1/8 when DB0 = 0 and 1/6 when DB0 = 1 Incrementing column address During a write: +1 During a read: 0 Releases the read-modify-write state. Internal reset Selects the common output scanning direction. Forward when DB3 = 0 Reverse when DB3 = 1 Selects the operating state of the internal power supply. Set the lower 3 bits. Selects the internal resistor ratio. Set the lower 3 bits. 1 1 1 1 0 1 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 4 5 6 7 10 LCD All-on display display) ON 11 LCD bias set 10100011 12 13 14 15 Read-modify-write End Reset Common output state select 11100000 11101110 11100010 11000 *** 11001 *** 00101 Operating state 00100 Resistance ratio setting 16 17 Power control set Voltage V1 adjustment internal resistance ratio set 40/74 PEDL9051G-01 OKI Semiconductor ML9051G No Operation DBn 76543210 10000001 * * Electronic potentiometer value A0 0 0 RD WR Comment Sets a 6-bit data in the electronic potentiometer register to adjust the V1 output voltage. (2-byte command) Electronic potentiometer mode set 18 External potentiometer register set 1 1 0 0 Static indicator 19 OFF 10101100 10101101 * * * * * * State 11010*** 11011*** * * * Number of lines 0 0 0 0 0 0 1 1 1 1 1 1 0 0 0 0 0 0 OFF when DB0 = 0 ON when DB0 = 1 Sets the blinking state. (2-byte command) Frame reversal when DB3 = 0. Line reversal when DB3 = 1 Sets the number (2-byte command) of line reversal. Compound command of Display OFF and Display all-on. ON Static indicator register set LCD drive method set Line reversal number set Power save NOP Test 20 1) 21 22 23 11100011 1111* * * * 0 0 1 1 0 0 The "No Operation" command. The command for factory testing of the IC chip. *: Invalid data (input: Don't care, output: Unknown) Note 1: When the line reversal drive is set, the ML9051G is not used in a multiple chip configuration. 41/74 PEDL9051G-01 OKI Semiconductor ML9051G DESCRIPTIONS OF OPERATION Display ON/OFF (Write) This is the command for controlling the turning on or off the LCD panel. The LCD display is turned on when a "1" is written in bit DB0 and is turned off when a "0" is written in this bit. A0 Display ON Display OFF 0 0 DB7 1 1 DB6 0 0 DB5 1 1 DB4 0 0 DB3 1 1 DB2 1 1 DB1 1 1 DB0 1 0 Display start line set (Write) This command specifies the display starting line address in the display data RAM. Normally, the topmost line in the display is specified using the display start line set command. It is possible to scroll the display screen by dynamically changing the address using the display start line set command. Line address 0 1 2 ... A0 0 0 0 ... DB7 0 0 0 ... DB6 1 1 1 ... DB5 0 0 0 ... DB4 0 0 0 ... DB3 0 0 0 ... DB2 0 0 0 ... DB1 0 0 1 ... DB0 0 1 0 ... 62 63 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 0 1 42/74 PEDL9051G-01 OKI Semiconductor ML9051G Page address set (Write) This command specifies the page address which corresponds to the lower address when accessing the display data RAM from the MPU side. It is possible to access any required bit in the display data RAM by specifying the page address and the column address. Page address 0 1 2 ... A0 0 0 0 ... DB7 1 1 1 ... DB6 0 0 0 ... DB5 1 1 1 ... DB4 1 1 1 ... DB3 0 0 0 ... DB2 0 0 0 ... DB1 0 0 1 ... DB0 0 1 0 ... 7 8 0 0 1 1 0 0 1 1 1 1 0 1 1 0 1 0 1 0 Note: Do not specify values that do not exist as an address. Column address set (Write) This command specifies the column address of the display data RAM. The column address is specified by successively writing the upper 4 bits and the lower 4 bits. Since the column address is automatically incremented (by + 1) every time the display data RAM is accessed, the MPU can read or write the display data continuously. The incrementing of the column address is stopped at the address 83(H). A0 Upper bits Lower bits 0 0 DB7 0 0 DB6 0 0 DB5 0 0 DB4 1 0 DB3 a7 a3 DB2 a6 a2 DB1 a5 a1 DB0 a4 a0 Column address 0 1 2 ... a7 0 0 0 ... a6 0 0 0 ... a5 0 0 0 ... a4 0 0 0 ... a3 0 0 0 ... a2 0 0 0 ... a1 0 0 1 ... a0 0 1 0 ... 130 131 1 1 0 0 0 0 0 0 0 0 0 0 1 1 0 1 Note: Do not specify values that do not exist as an address. 43/74 PEDL9051G-01 OKI Semiconductor ML9051G Status read (Read) A0 0 DB7 BUSY DB6 ADC DB5 ON/OFF DB4 RESET DB3 * DB2 * DB1 * DB0 * *: Invalid data When BUSY is '1', it indicates that the internal operations are being made or the LSI is being reset. Although no command is accepted until BUSY becomes '0', there is no need to check this bit if the cycle time can be satisfied. This bit indicates the relationship between the column address and the segment driver. ADC 0: Reverse (SEG131 SEG0); column address 0(H) 83(H) 1: Forward (SEG0 SEG131); column address 0(H) 83(H) (Opposite to the polarity of the ADC command.) This bit indicates the ON/OFF state of the display. (Opposite to the polarity of the display ON/OFF command.) 0: Display ON 1: Display OFF This bit indicates that the LSI is being reset due to the RES signal or the reset command. 0: Operating state 1: Being reset BUSY ON/OFF RESET Display data write (Write) This command writes an 8-bit data at the specified address of the display data RAM. Since the column address is automatically incremented (by +1) after writing the data, the MPU can write successive display data to the display data RAM. A0 1 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 Write data Display data read (Read) This command read the 8-bit data from the specified address of the display data RAM. Since the column address is automatically incremented (by +1) after reading the data, the MPU can read successive display data from the display data RAM. Further, one dummy read operation is necessary immediately after setting the column data. The display data cannot be read out when the serial interface is being used. A0 1 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 Read data 44/74 PEDL9051G-01 OKI Semiconductor ML9051G ADC select (segment driver direction select) (Write) Using this command it is possible to reverse the relationship of correspondence between the column address of the display data RAM and the segment driver output. It is possible to reverse the sequence of the segment driver output pin by the command. A0 Forward Reverse 0 0 DB7 1 1 DB6 0 0 DB5 1 1 DB4 0 0 DB3 0 0 DB2 0 0 DB1 0 0 DB0 0 1 Forward/reverse display mode (Write) It is possible to toggle the display on and off condition without changing the contents of the display data RAM. In this case, the contents of the display data RAM will be retained. A0 Forward Reverse 0 0 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 1 1 0 0 1 1 0 0 0 0 1 1 1 1 0 1 RAM Data Display on when "H" Display on when "L" LCD display all-on ON/OFF (Write) Using this command, it is possible to forcibly turn ON all the dots in the display irrespective of the contents of the display data RAM. In this case, the contents of the display data RAM will be retained. This command is given priority over the Forward/reverse display mode command. A0 All-on display OFF (Normal display) All-on display ON 0 0 DB7 1 1 DB6 0 0 DB5 1 1 DB4 0 0 DB3 0 0 DB2 1 1 DB1 0 0 DB0 0 1 The power save mode will be entered into when the Display all-on ON command is executed in the display OFF condition. LCD bias set (Write) This command is used for selecting the bias ratio of the voltage necessary for driving the LCD device or panel. LCD bias 1/8 bias 1/6 bias A0 0 0 DB7 1 1 DB6 0 0 DB5 1 1 DB4 0 0 DB3 0 0 DB2 0 0 DB1 1 1 DB0 0 1 45/74 PEDL9051G-01 OKI Semiconductor ML9051G Read modify write (Write) This command is used in combination with the End command. When this command is issued once, the column address is not changed when the Display data read command is issued, but is incremented (by +1) only when the Display data write command is issued. This condition is maintained until the End command is issued. When the End command is issued, the column address is restored to the address that was effective at the time the Read-modify-write command was issued last. Using this function, it is possible to reduce the overhead on the MPU when repeatedly changing the data in special display area such as a blinking cursor. A0 0 DB7 1 DB6 1 DB5 1 DB4 0 DB3 0 DB2 0 DB1 0 DB0 0 End (Write) This command releases the read-modify-write mode and restores the column address to the value at the beginning of the mode. A0 0 DB7 1 DB6 1 DB5 1 DB4 0 DB3 1 DB2 1 DB1 1 DB0 0 Restored Column address N N+1 N+2 N+3 .... N+m N End Read-modify-write mode set Reset (Write) This command initializes the display start line number, column address, page address, common output state, voltage V1 adjustment internal resistor ratio, electronic potentiometer function, and the static indicator function, and also releases the read-modify-write mode or the test mode. This command does not affect the contents of the display data RAM. The reset operation is made after issuing the reset command. The initialization after switching on the power is carried out by the reset signal input to the RES pin. A0 0 DB7 1 DB6 1 DB5 1 DB4 0 DB3 0 DB2 0 DB1 1 DB0 0 Common output state select (Write) This command is used for selecting the scanning direction of the common output pins. Scanning direction Forward Reverse COM0 COM47 COM47 COM0 A0 0 0 DB7 1 1 DB6 1 1 DB5 0 0 DB4 0 0 DB3 0 1 DB2 * * DB1 * * DB0 * * *: Invalid data 46/74 PEDL9051G-01 OKI Semiconductor ML9051G Power control set (Write) This command set the functions of the power supply circuits. A0 Voltage multiplier circuit: OFF Voltage multiplier circuit: ON Voltage adjustment circuit: OFF Voltage adjustment circuit: ON Voltage follower circuits: OFF Voltage follower circuits: ON 0 0 0 0 0 0 DB7 0 0 0 0 0 0 DB6 0 0 0 0 0 0 DB5 1 1 1 1 1 1 DB4 0 0 0 0 0 0 DB3 1 1 1 1 1 1 DB2 0 1 0 1 0 1 DB1 DB0 Voltage V1 adjustment internal resistor ratio set This command sets the ratios of the internal resistors for adjusting the voltage V1. Resistor ratio 3.0 3.5 4.0 4.5 5.0 5.5 6.0 Input inhibiting code A0 0 0 0 0 0 0 0 0 DB7 0 0 0 0 0 0 0 0 DB6 0 0 0 0 0 0 0 0 DB5 1 1 1 1 1 1 1 1 DB4 0 0 0 0 0 0 0 0 DB3 0 0 0 0 0 0 0 0 DB2 0 0 0 0 1 1 1 1 DB1 0 0 1 1 0 0 1 1 DB0 0 1 0 1 0 1 0 1 Note: Because this LSI has temperature gradient, V1 rises at lower temperatures. When using V1 gain of 6 times, adjust the built-in electronic potentiometer so that V1 does not exceed 18 V. Electronic potentiometer (2-byte command) This command is used for controlling the LCD drive voltage V1 output by the voltage adjustment circuit of the internal LCD power supply and for adjusting the intensity of the LCD display. This is a two-byte command consisting of the Electronic potentiometer mode set command and the Electronic potentiometer register set command, both of which should always be issued successively as a pair. * Electronic potentiometer mode set (Write) When this command is issued, the electronic potentiometer register set command becomes effective. Once the electronic potentiometer mode is set, it is not possible to issue any command other than the Electronic potentiometer register set command. This condition is released after data has been set in the register using the Electronic potentiometer register set command. A0 0 DB7 1 DB6 0 DB5 0 DB4 0 DB3 0 DB2 0 DB1 0 DB0 1 47/74 PEDL9051G-01 OKI Semiconductor ML9051G * Electronic potentiometer register set (Write) By setting a 6-bit data in the electronic potentiometer register using this command, it is possible to set the LCD drive voltage V1 to one of the 64 voltage levels. The electronic potentiometer mode is released after some data has been set in the electronic potentiometer register using this command. 63 62 61 60 ... A0 0 0 0 0 ... DB7 * * * * ... DB6 * * * * ... DB5 0 0 0 0 ... DB4 0 0 0 0 ... DB3 0 0 0 0 ... DB2 0 0 0 0 ... DB1 0 0 1 1 ... DB0 1 1 0 1 ... ... ... 1 0 ... 1 1 1 1 1 1 1 1 1 1 0 1 0 * * *: Invalid data Set the data (*, *, 1, 0, 0, 0, 0, 0) when not using the electronic potentiometer function. Sequence of setting the electronic potentiometer register: Electronic potentiometer mode set Electronic potentiometer register set The electronic potentiometer mode is released Static indicator (2-byte command) This command is used for controlling the static drive type indicator display. Static indicator display is controlled only by this command and is independent of all other display control commands. Since the Static indicator ON command is a two-byte command used in combination with the static indictor register set command, these two commands should always be used together. (The Static indicator OFF command is a single byte command.) 48/74 PEDL9051G-01 OKI Semiconductor ML9051G * Static indicator ON/OFF (Write) When the Static indicator ON command is issued, the Static indicator register set command becomes effective. Once the Static indicator ON command is issued, it is not possible to issue any command other than the Static indicator register set command. This condition is released only after some data is written into the register using the static indicator register set command. Static indicator OFF ON A0 0 0 DB7 1 1 DB6 0 0 DB5 1 1 DB4 0 0 DB3 1 1 DB2 1 1 DB1 0 0 DB0 0 1 * Static indicator register set (Write) This command is used to set data in the 2-bit static indicator register thereby setting the blinking state of the static indicator. Indicator OFF ON(Blinking at about 1sec intervals) ON(Blinking at about 0.5sec intervals) ON(Continuously ON) A0 0 0 0 0 DB7 * * * * DB6 * * * * DB5 * * * * DB4 * * * * DB3 * * * * DB2 * * * * DB1 0 0 1 1 DB0 0 1 0 1 *: Invalid data Sequence of setting the static indicator register: Static indicator ON Static indicator register set The static indicator mode is released 49/74 PEDL9051G-01 OKI Semiconductor ML9051G LCD drive method set (Write) This command sets the LCD drive method. * Line reversal drive (2-byte command)/frame reversal drive select Line or frame reversal drive can be selected as the LCD drive method. When selecting line reversal drive, which is 2-byte command used with line reversal number set command, be sure to use both commands successively. Once line reversal drive is set, commands other than line reversal number set command cannot be used. This state is released after data is set to the register by line reversal number set command. The frame reversal set command is a single byte command. LCD drive method Frame reversal Line reversal A0 0 0 DB7 1 1 DB6 1 1 DB5 0 0 DB4 1 1 DB3 0 1 DB2 * * DB1 * * DB0 * * *: Invalid data * Line reversal number set (Write) The number of lines is set when the line reversal is set using the LCD drive method set command. Number of line reversal 1 2 3 4 ... A0 0 0 0 0 ... DB7 * * * * ... DB6 * * * * ... DB5 * * * * ... DB4 0 0 0 0 ... DB3 0 0 0 0 ... DB2 0 0 0 0 ... DB1 0 0 1 1 ... DB0 0 1 0 1 ... ... ... ... 31 32 ... 1 1 1 1 1 1 1 1 0 1 0 * * * *: Invalid data LCD drive method set Number of line is set in case of line reversal Note 1: Note 2: Because the number of line reversal depends on panel size and panel load capacitance, set the optimum number of lines at the time of ES evaluation. When line reversal drive is used, a multiple chip configuration cannot be achieved. 50/74 PEDL9051G-01 OKI Semiconductor ML9051G Power save (Compound command) The LSI goes into the power save state when the Display all-on ON command is issued when the LSI is in the display OFF state, and it is possible to greatly reduce the current consumption in this state. The power save state is of two types, namely, the sleep state and the standby state, and the LSI goes into the standby state when the static indicator has been made ON. The display data and the operating mode just before entering the power save mode are retained in both the sleep state and the standby state, and also the MPU can access the display data RAM and other registers in these states. The power save mode is released by issuing the Display all-on OFF command. (See the following figure.) Static indicator OFF Static indicator ON Power save command issue (compound command) Sleep state Power save OFF command (Display all-on OFF command) Standby state Power save OFF command (Display all-on OFF command) Standby state released Sleep state released 51/74 PEDL9051G-01 OKI Semiconductor ML9051G * Sleep state In this state, all the operations of the LCD display system are stopped and it is possible to reduce the current consumption to a level near the idle state current consumption unless there are accesses from the MPU. The internal conditions in the sleep state are as follows: (1) The oscillator circuit and the LCD power supply are stopped. (2) All the LCD drive circuits are stopped and the segment and common driver outputs will be at the VSS level. * Standby state All operations of the dynamic LCD display section are stopped, only the static display circuits for the indicators operate and hence the current consumption will be the minimum necessary for static drive. The internal conditions in the standby state are as follows: (1) The power supply circuit for LCD drive is stopped. The oscillator circuit will be operating. (2) The LCD drive circuits for dynamic display are stopped and the segment and common driver outputs will be at the VSS level. The static display section will be operating. Note: When using an external power supply, stop external power supply at power save start-up. For example, when providing each level of LCD drive voltage with external voltage divider, add a circuit for cutting off current flowing through the resistors of the voltage divider when initiating power save. The ML9051G has LCD display blanking control pin, DOF, which goes "L" at power save start-up. The external power supply can be stopped using DOF output. NOP (Write) This is a No Operation command. A0 0 DB7 1 DB6 1 DB5 1 DB4 0 DB3 0 DB2 0 DB1 1 DB0 1 Test (Write) This is a command for testing the IC chip. Do not use this command. When the test command is issued by mistake, this state can be released by issuing a NOP command. This command will be ineffective if the TEST0 pin is open or at the "L" level. A0 0 DB7 1 DB6 1 DB5 1 DB4 1 DB3 * DB2 * DB1 * DB0 * *: Invalid data 52/74 PEDL9051G-01 OKI Semiconductor ML9051G Initialized condition using the RES pin This LSI goes into the initialized condition when the RES input goes to the "L" level. The initialized condition consists of the following conditions. (1) Display OFF (2) Forward display mode (3) ADC select: Incremented (ADC command DB0 = "L") (4) Power control register: (DB2, DB1, DB0) = (0, 0, 0) (5) The registers and data in the serial interface are cleared. (6) LCD Power supply bias ratio: 1/8 bias (7) All display dots OFF (8) Read-modify-write: OFF (9) Static indicator: OFF Static indicator register: (DB1, DB0) = (0, 0) (10) Line 1 is set as the display start line. (11) The column address is set to address 0. (12) The page address is set to 0. (13) Common output state: Forward (14) Voltage V1 adjustment internal resistor ratio register: (DB2, DB1, DB0) = (1, 0, 0) (15) The electronic potentiometer register set mode is released. Electronic potentiometer register: (DB5, DB4, DB3, DB2, DB1, DB0) = (1, 0, 0 ,0, 0, 0) (16) The LCD drive method is set to the frame reversal drive. Line reversal number register: (DB4, DB3, DB2, DB1, DB0) = (1, 0, 0, 0, 0) On the other hand, when the reset command is used, only the conditions (8) to (15) above are set. As is shown in the "MPU Interface (example for reference)", the RES pin is connected to the Reset pin of the MPU and the initialization of this LSI is made simultaneously with the resetting of the MPU. This LSI always has to be reset using the RES pin at the time the power is switched ON. Also, excessive current can flow through this LSI when the control signal from the MPU is in the high impedance state. It is necessary to take measures to ensure that the input pins of this LSI do not go into the high impedance state after the power has been switched ON. When the built-in LCD drive power supply circuit of the ML9051G is not used, it is necessary that RES = "L" when the external LCD drive power supply goes ON. During the period when RES = "L", although the oscillator circuit is operating, the display timing generator would have stopped and the pins CL, FR, FRS, and DOF would have been tied to the "H" level. There is no effect on the pins DB0 to DB7. 53/74 PEDL9051G-01 OKI Semiconductor ML9051G EXAMPLES OF SETTINGS FOR THE INSTRUCTIONS When using the internal power supply immediately after power-on VDD-VSS Power supply ON when the pin RES = "L" Power supply stabilization Release reset state (RES Pin = "H") Initial settings state (default) *1 Function setting using command input (user settings) *2 LCD bias set *3 ADC select *4 Common output state select *5 Line reversal/frame reversal drive select *(a) Function setting using command input (user settings) Setting voltage V1 adjustment internal resistor ratio *6 Electronic potentiometer *7 Function stabilization using command input (user settings) Power control set *8 Wait for more than 300 ms Initial setting state complete *(b) *(a): Carry out power control set within 5ms after releasing the reset state. The 5ms duration changes depending on the panel characteristics and the value of the smoothing capacitor. We recommend verification of operation using an actual unit. *(b): When trace resistance in COG mounting does not exist, wait for over 300 ms. Since this value varies with trace resistance, V1, smoothing capacitors, or voltage multiplier capacitors in COG mounting, confirm operation on an actual circuit board when using this LSI. Notes: *1: *2: *3: *4: *5: *6: *7: *8: Sections to be referred to Functional description "Reset circuit" Description of operation "LCD bias set" Description of operation "ADC select" Description of operation "Common output state select" Description of operation "Line reversal/frame reversal drive select" Functional description "Power supply circuit", Operation description "Voltage V1 adjustment internal resistor ratio set" Functional description "Power supply circuit", Description of operation "Electronic potentiometer" Functional description "Power supply circuit", Description of operation "Power control set" 54/74 PEDL9051G-01 OKI Semiconductor ML9051G When not using the internal power supply immediately after power-on VDD-VSS Power supply ON when the pin RES = "L" Power supply stabilization Release reset state (RES Pin = "H") Initial settings state (default) *1 *(a) Start power save mode (compound command) *9 Function setting using command input (user settings) *2 LCD bias set *3 ADC select *4 Common output state select *5 Line reversal/frame reversal drive select Function setting using command input (user settings) Setting voltage V1 adjustment internal resistor ratio *6 Electronic potentiometer *7 Power save OFF *9 Function setting using command input (user settings) Power control set *8 Wait for more than 300 ms Initial setting state complete *(b) *(c) *(a): Enter the power save state within 5ms after releasing the reset state. *(b): Carry out power control set within 5ms after releasing the power save state. The 5ms duration in *(a) and *(b) changes depending on the panel characteristics and the value of the smoothing capacitor. We recommend verification of operation using an actual unit. *(c): When trace resistance in COG mounting does not exist, wait for over 300 ms. Since this value varies with trace resistance, V1, smoothing capacitors, or voltage multiplier capacitors in COG mounting, confirm operation on an actual circuit board when using this LSI. Notes: *1: *2: *3: *4: *5: *6: *7: *8: *9: Sections to be referred to Functional description "Reset circuit" Description of operation "LCD bias set" Description of operation "ADC select" Description of operation "Common output state select" Description of operation "Line reversal/frame reversal drive select" Functional description "Power supply circuit", Description of operation "Voltage V1 adjustment internal resistor ratio set" Functional description "Power supply circuit", Description of operation "Electronic potentiometer" Functional description "Power supply circuit", Description of operation "Power control set" The power save state can be either the sleep state or the standby state. Description of operation "Power save (compound command)" 55/74 PEDL9051G-01 OKI Semiconductor ML9051G Data display End of initial settings Function stabilization using command input (user settings) Display start line set *10 Function stabilization using command input (user settings) Page address set *11 Function stabilization using command input (user settings) Column address set *12 Function stabilization using command input (user settings) Display data write No No End of page write? *13 Yes End of display data write? Yes Function stabilization using command input (user settings) Display ON/OFF End of data display *14 Notes: *10: *11: *12: *13: *14: Sections to be referred to Description of operation "Display start line set" Description of operation "Page address set" Description of operation "Column address set" Description of operation "Display data write" Description of operation "Display ON/OFF" 56/74 PEDL9051G-01 OKI Semiconductor ML9051G Power supply OFF (*15) Any state Function stabilization using command input (user settings) Power save *16 VDD-VSS Power supply OFF Notes: *15: *16: Sections to be referred to The power supply of this LSI is switched OFF after switching OFF the internal power supply. Function description "Power supply circuit" If the power supply of this LSI is switched OFF when the internal power supply is still ON, since the state of supplying power to the built-in LCD drive circuits continues for a short duration, it may affect the display quality of the LCD panel. Always follow the power supply switching OFF sequence. Description of operation "Power save" Refresh Although the ML9051G holds operation state by commands, excessive external noise might change the internal state. On a chip-mounting and system level, it is necessary to take countermeasures against preventing noise from occurring. It is recommended to use the refresh sequence periodically to control sudden noise. Refresh sequence Set to the state in which all commands have been set. Test mode release command (E3(H)) Refresh RAM 57/74 PEDL9051G-01 OKI Semiconductor ML9051G MPU INTERFACE The ML9051G series ICs can be connected directly to the 80-series and 68-series MPUs. Further, by using the serial interface, it is possible to operate the LSI with a minimum number of signal lines. In addition, it is possible to expand the display area by using the ML9051G series LSIs in a multiple chip configuration. In this case, it is possible to select the individual LSI to be accessed using the chip select signals. * 80-Series MPU VDD VCC A0 A1 to A7 IORQ MPU Decoder A0 CS1 CS2 VDD C86 DB0 to DB7 RD WR RES DB0 to DB7 RD WR RES RESET ML9051G GND VSS P/S VSS * 68-Series MPU VDD VCC A0 A1 to A15 VMA MPU A0 CS1 Decoder CS2 VDD C86 DB0 to DB7 E R/W RES DB0 to DB7 E R/W RES RESET ML9051G GND VSS P/S VSS * Serial interface VDD VCC Port 3 Port 4 Port 5 MPU A0 CS1 CS2 SI SCL RES RESET VDD C86 ML9051G Can be tied to either level. Port1 Port2 RES GND VSS P/S VSS 58/74 PEDL9051G-01 OKI Semiconductor ML9051G PAD CONFIGURATION Pad Layout Chip Size : 10.95 x 3.46 mm Pad Coordinates Pad No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 Pad Name DUMMY DUMMY DUMMY DUMMY FRS FR CL DOF X (m) -5000 -4888 -4776 -4664 -4552 -4440 -4328 -4216 -4104 -3992 -3880 -3768 -3656 -3544 -3432 -3320 -3208 -3096 -2984 -2872 Y (m) -1550 -1550 -1550 -1550 -1550 -1550 -1550 -1550 -1550 -1550 -1550 -1550 -1550 -1550 -1550 -1550 -1550 -1550 -1550 -1550 Pad No. 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 Pad Name DB1 DB2 DB3 DB4 DB5 DB6 DB7 VDD VDD VDD VDD VIN VIN VIN VIN VSS VSS VSS VOUT VOUT X (m) -2760 -2648 -2536 -2424 -2312 -2200 -2088 -1976 -1896 -1816 -1736 -1656 -1576 -1496 -1416 -1336 -1256 -1176 -1076 -951 Y (m) -1550 -1550 -1550 -1550 -1550 -1550 -1550 -1550 -1550 -1550 -1550 -1550 -1550 -1550 -1550 -1550 -1550 -1550 -1550 -1550 TEST0 VSS CS1 CS2 VDD RES A0 VSS WR RD VDD DB0 Note: Leave DUMMY pads open. 59/74 PEDL9051G-01 OKI Semiconductor ML9051G Pad No. 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 Pad Name VC6+ VC6+ DUMMY DUMMY VC4+ VC4+ VS2- VS2- VS1- VS1- VC5+ VC5+ VC3+ VC3+ DUMMY DUMMY VSS VSS VRS VRS VDD VDD V1 V1 V2 V2 V3 V3 V4 V4 V5 V5 VR VR VDD VDD TEST1 VDD M/S CLS X (m) -826 -701 -576 -451 -326 -201 -76 49 174 299 424 549 674 799 924 1049 1174 1299 1424 1549 1674 1799 1924 2049 2174 2299 2424 2549 2674 2799 2924 3049 3174 3299 3424 3549 3674 3786 3898 4010 Y (m) -1550 -1550 -1550 -1550 -1550 -1550 -1550 -1550 -1550 -1550 -1550 -1550 -1550 -1550 -1550 -1550 -1550 -1550 -1550 -1550 -1550 -1550 -1550 -1550 -1550 -1550 -1550 -1550 -1550 -1550 -1550 -1550 -1550 -1550 -1550 -1550 -1550 -1550 -1550 -1550 Pad No. 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 Pad Name VSS C86 P/S VDD HPM X (m) 4122 4234 4346 4458 4570 4682 4794 4906 5018 5130 5340 5340 5340 5340 5340 5340 5340 5340 5340 5340 5340 5340 5340 5340 5340 5340 5340 5340 5340 5340 5340 5340 5340 5340 5340 5340 5340 5340 5340 5340 Y (m) -1550 -1550 -1550 -1550 -1550 -1550 -1550 -1550 -1550 -1550 -1363.2 -1298.2 -1233.2 -1168.2 -1103.2 -1038.2 -973.2 -908.2 -843.2 -778.2 -713.2 -648.2 -583.2 -518.2 -453.2 -388.2 -323.2 -258.2 -193.2 -128.2 -63.2 1.8 66.8 131.8 196.8 261.8 326.8 391.8 456.8 521.8 VSS IRS VDD DUMMY DUMMY DUMMY DUMMY DUMMY DUMMY DUMMY DUMMY DUMMY DUMMY DUMMY DUMMY DUMMY DUMMY DUMMY DUMMY DUMMY COM23 COM22 COM21 COM20 COM19 COM18 COM17 COM16 COM15 COM14 COM13 COM12 COM11 COM10 COM9 Note: Leave DUMMY pads open. 60/74 PEDL9051G-01 OKI Semiconductor ML9051G Pad No. 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 Pad Name COM8 COM7 COM6 COM5 COM4 COM3 COM2 COM1 COM0 COMS1 DUMMY DUMMY DUMMY DUMMY DUMMY DUMMY DUMMY DUMMY DUMMY DUMMY DUMMY DUMMY DUMMY DUMMY DUMMY SEG0 SEG1 SEG2 SEG3 SEG4 SEG5 SEG6 SEG7 SEG8 SEG9 SEG10 SEG11 SEG12 SEG13 SEG14 X (m) 5340 5340 5340 5340 5340 5340 5340 5340 5340 5340 5340 5340 5340 5037.5 4972.5 4907.5 4842.5 4777.5 4712.5 4647.5 4582.5 4517.5 4452.5 4387.5 4322.5 4257.5 4192.5 4127.5 4062.5 3997.5 3932.5 3867.5 3802.5 3737.5 3672.5 3607.5 3542.5 3477.5 3412.5 3347.5 Y (m) 586.8 651.8 716.8 781.8 846.8 911.8 976.8 1041.8 1106.8 1171.8 1236.8 1301.8 1366.8 1545 1545 1545 1545 1545 1545 1545 1545 1545 1545 1545 1545 1545 1545 1545 1545 1545 1545 1545 1545 1545 1545 1545 1545 1545 1545 1545 Pad No. 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 Pad Name SEG15 SEG16 SEG17 SEG18 SEG19 SEG20 SEG21 SEG22 SEG23 SEG24 SEG25 SEG26 SEG27 SEG28 SEG29 SEG30 SEG31 SEG32 SEG33 SEG34 SEG35 SEG36 SEG37 SEG38 SEG39 SEG40 SEG41 SEG42 SEG43 SEG44 SEG45 SEG46 SEG47 SEG48 SEG49 SEG50 SEG51 SEG52 SEG53 SEG54 X (m) 3282.5 3217.5 3152.5 3087.5 3022.5 2957.5 2892.5 2827.5 2762.5 2697.5 2632.5 2567.5 2502.5 2437.5 2372.5 2307.5 2242.5 2177.5 2112.5 2047.5 1982.5 1917.5 1852.5 1787.5 1722.5 1657.5 1592.5 1527.5 1462.5 1397.5 1332.5 1267.5 1202.5 1137.5 1072.5 1007.5 942.5 877.5 812.5 747.5 Y (m) 1545 1545 1545 1545 1545 1545 1545 1545 1545 1545 1545 1545 1545 1545 1545 1545 1545 1545 1545 1545 1545 1545 1545 1545 1545 1545 1545 1545 1545 1545 1545 1545 1545 1545 1545 1545 1545 1545 1545 1545 Note: Leave DUMMY pads open. 61/74 PEDL9051G-01 OKI Semiconductor ML9051G Pad No. 201 202 203 204 205 206 207 208 209 210 211 212 213 214 215 216 217 218 219 220 221 222 223 224 225 226 227 228 229 230 231 232 233 234 235 236 237 238 239 240 Pad Name SEG55 SEG56 SEG57 SEG58 SEG59 SEG60 SEG61 SEG62 SEG63 SEG64 SEG65 SEG66 SEG67 SEG68 SEG69 SEG70 SEG71 SEG72 SEG73 SEG74 SEG75 SEG76 SEG77 SEG78 SEG79 SEG80 SEG81 SEG82 SEG83 SEG84 SEG85 SEG86 SEG87 SEG88 SEG89 SEG90 SEG91 SEG92 SEG93 SEG94 X (m) 682.5 617.5 552.5 487.5 422.5 357.5 292.5 227.5 162.5 97.5 32.5 -32.5 -97.5 -162.5 -227.5 -292.5 -357.5 -422.5 -487.5 -552.5 -617.5 -682.5 -747.5 -812.5 -877.5 -942.5 -1007.5 -1072.5 -1137.5 -1202.5 -1267.5 -1332.5 -1397.5 -1462.5 -1527.5 -1592.5 -1657.5 -1722.5 -1787.5 -1852.5 Y (m) 1545 1545 1545 1545 1545 1545 1545 1545 1545 1545 1545 1545 1545 1545 1545 1545 1545 1545 1545 1545 1545 1545 1545 1545 1545 1545 1545 1545 1545 1545 1545 1545 1545 1545 1545 1545 1545 1545 1545 1545 Pad No. 241 242 243 244 245 246 247 248 249 250 251 252 253 254 255 256 257 258 259 260 261 262 263 264 265 266 267 268 269 270 271 272 273 274 275 276 277 278 279 280 Pad Name SEG95 SEG96 SEG97 SEG98 SEG99 SEG100 SEG101 SEG102 SEG103 SEG104 SEG105 SEG106 SEG107 SEG108 SEG109 SEG110 SEG111 SEG112 SEG113 SEG114 SEG115 SEG116 SEG117 SEG118 SEG119 SEG120 SEG121 SEG122 SEG123 SEG124 SEG125 SEG126 SEG127 SEG128 SEG129 SEG130 SEG131 DUMMY DUMMY DUMMY X (m) -1917.5 -1982.5 -2047.5 -2112.5 -2177.5 -2242.5 -2307.5 -2372.5 -2437.5 -2502.5 -2567.5 -2632.5 -2697.5 -2762.5 -2827.5 -2892.5 -2957.5 -3022.5 -3087.5 -3152.5 -3217.5 -3282.5 -3347.5 -3412.5 -3477.5 -3542.5 -3607.5 -3672.5 -3737.5 -3802.5 -3867.5 -3932.5 -3997.5 -4062.5 -4127.5 -4192.5 -4257.5 -4322.5 -4387.5 -4452.5 Y (m) 1545 1545 1545 1545 1545 1545 1545 1545 1545 1545 1545 1545 1545 1545 1545 1545 1545 1545 1545 1545 1545 1545 1545 1545 1545 1545 1545 1545 1545 1545 1545 1545 1545 1545 1545 1545 1545 1545 1545 1545 Note: Leave DUMMY pads open. 62/74 PEDL9051G-01 OKI Semiconductor ML9051G Pad No. 281 282 283 284 285 286 287 288 289 290 291 292 293 294 295 296 297 298 299 300 301 302 303 304 305 306 307 Pad Name DUMMY DUMMY DUMMY DUMMY DUMMY DUMMY DUMMY DUMMY DUMMY DUMMY DUMMY DUMMY DUMMY DUMMY COM24 COM25 COM26 COM27 COM28 COM29 COM30 COM31 COM32 COM33 COM34 COM35 COM36 X (m) -4517.5 -4582.5 -4647.5 -4712.5 -4777.5 -4842.5 -4907.5 -4972.5 -5037.5 -5102.5 -5167.5 -5340 -5340 -5340 -5340 -5340 -5340 -5340 -5340 -5340 -5340 -5340 -5340 -5340 -5340 -5340 -5340 Y (m) 1545 1545 1545 1545 1545 1545 1545 1545 1545 1545 1545 1366.8 1301.8 1236.8 1171.8 1106.8 1041.8 976.8 911.8 846.8 781.8 716.8 651.8 586.8 521.8 456.8 391.8 Pad No. 308 309 310 311 312 313 314 315 316 317 318 319 320 321 322 323 324 325 326 327 328 329 330 331 332 333 334 Pad Name COM37 COM38 COM39 COM40 COM41 COM42 COM43 COM44 COM45 COM46 COM47 COMS0 DUMMY DUMMY DUMMY DUMMY DUMMY DUMMY DUMMY DUMMY DUMMY DUMMY DUMMY DUMMY DUMMY DUMMY DUMMY X (m) -5340 -5340 -5340 -5340 -5340 -5340 -5340 -5340 -5340 -5340 -5340 -5340 -5340 -5340 -5340 -5340 -5340 -5340 -5340 -5340 -5340 -5340 -5340 -5340 -5340 -5340 -5340 Y (m) 326.8 261.8 196.8 131.8 66.8 1.8 -63.2 -128.2 -193.2 -258.2 -323.2 -388.2 -453.2 -518.2 -583.2 -648.2 -713.2 -778.2 -843.2 -908.2 -973.2 -1038.2 -1103.2 -1168.2 -1233.2 -1298.2 -1363.2 Note: Leave DUMMY pads open. 63/74 PEDL9051G-01 OKI Semiconductor ML9051G ML9051G GOLD BUMP SPECIFICATION Gold Bump Specification Symbol A B C D E F G H I J K L M N O P Q R S Parameter Bump Pitch (Min. Section) Bump Size (Segment Section: Pitch Direction) Bump Size (Segment Section: Depth Direction) Bump-to-Bump Distance (Segment Section: Pitch Direc MIN. 65 38 93 17 93 38 63 83 53 83 83 83 73 73 --- 10 --- --- 26 30 TYP. --- 43 98 22 98 43 68 88 58 88 88 88 78 78 --- 15 --- --- --- --- MAX. --- 48 103 27 103 48 73 93 63 93 93 93 83 83 2 20 3 5 --- 80 Unit m m m m m m m m m m m m m m m m m m g Hv Bump Size (Common Section: Pitch Direction) Bump Size (Common Section: Depth Direction) Bump size (Input Section 1: Pitch Direction) Bump size (Input Section 1: Depth Direction) Bump size (Input Section 2: Pitch Direction) Bump size (Input Section 2: Depth Direction) Bump size (Input Section 3: Pitch Direction) Bump size (Input Section 3: Depth Direction) Bump Size (For Alignment: Pitch Direction) Bump Size (For Alignment: Depth Direction) Drift of Bump Total Pitch Bump Height Bump Height Dispersion Inside Chip (Range) Bump Edge Height Shear Strength (g) Bump Hardness (Hv: 25 g load) Top View and Cross Section View A B*E*G*I*K*M Q C*F*H*J*L*N D Cross Section View Top View P 64/74 Alignment mark Alignment mark (50375, 1545) 133.0 m 73.0 m PAD body Segment section PAD size (Pin 134 to Pin 291) ML9051G Alignment Mark Layout Alignment mark size (Material: Aluminum pattern) (No bump) 98 m (Bump) 100.0 m 40.0 m (-51675, 1545) Alignment mark for bump 133.0 m OKI Semiconductor 100.0 m 110.0 m (Aluminum pattern) 115.7 m 100 m Aluminum pattern Bump Enlarged view 134 100 m Type 55.0 m (Aluminum pattern) 43 m (Bump) 138.7 m 133 Enlarged view 105.7 m (5340, 1366.8) 291 Common section PAD size (Pin 292 to Pin 334) (-5340. -1363.2) 3.46 mm 91 10.95 mm Input section PAD size (Pin 1 to Pin 27) 88 m (Bump) 88 m (Bump) Input section PAD size (Pin 28 to Pin 58) Input section PAD size (Pin 59 to Pin 77) Input section PAD size (Pin 78 to Pin 90) 88 m (Bump) 88 m (Bump) 125.0 m 90 Enlarged view 158.0 m (5130, -1550) 292 Common section PAD size (Pin 91 to Pin 133) 55.0 m (Aluminum pattern) 43 m (Bump) 110.0 m (Aluminum pattern) 43.0 m (Bump) 55.0 m (Aluminum pattern) 110.0 m (Aluminum pattern) 98 m (Bump) 98.0 m (Bump) (5340, -1363.2) 334 (-5340, -1363.2) 100.0 m (Aluminum pattern) 100.0 m (Aluminum pattern) 109.3 m 142.3 m 119.3 m Enlarged view 1 100.0 m 65.0 m 100.0 m (Aluminum pattern) 100.0 m (Aluminum pattern) 100 m 133.0 m 100 m 98.0 m (-5000, -1550) Alignment mark PEDL9051G-01 ML9051G 65/74 Alignment mark for bump Alignment mark 68 m 68 m 58 m 88 m 80.0 m 70.0 m 100.0 m 80.0 m (Bump) (Bump) (Aluminum pattern) (Aluminum pattern) (Bump) (Aluminum pattern) (Bump) (Aluminum pattern) PEDL9051G-01 OKI Semiconductor ML9051G REFERENCE DATA VIN = 4.8 V R VIN R VSS + C1 - R VOUT R + R R R VC6+ Dummy VC4+ VS2- VS1- VC5+ OPEN VC3+ ML9051G Chip I LOAD - C1 R = 0/100/400 C1 = 4.7F C1 - R + Equivalent circuit to 3-time voltage multiplier with trace resistances external to the COG-mounted chip ML9051G voltage multiplier load characteristics -Load current dependency at 3-time multiplication- 18.0 17.0 16.0 Evaluation conditions Tj = 85C Voltage multiplier capacitor C1 = 4.7 F VIN = 4.8 V, 3-time multiplication Only a voltage multiplier circuit operates by power control set command "2C". Voltage multiplier output voltage Vout [V] 15.0 14.0 13.0 12.0 11.0 10.0 R=0 R = 100 R = 400 9.0 8.0 7.0 6.0 0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 Load current ILoad [mA] 66/74 PEDL9051G-01 OKI Semiconductor ML9051G REFERENCE DATA VIN = 4.5 V R VIN R VSS + C1 - R VOUT R + VC6 + R + R R Dummy VC4 + VS2 - VS1 - VC5 + R VC3 + ML9051G Chip I LOAD - C1 C1 - R = 0 /100 /400 C1 = 4.7F C1 - R + Equivalent circuit to 4-time voltage multiplier with trace resistances external to the COG-mounted chip ML9051G voltage multiplier load characteristics -Load current dependency at 4-time multiplication- 18.0 17.0 16.0 15.0 Voltage multiplier capacitor C1 = 4.7 F VIN = 4.5 V, 4-time multiplication Only a voltage multiplier circuit operates by power control set command "2C". R=0 R = 100 R = 400 Evaluation conditions Tj = 85C Voltage multiplier output voltage Vout [V] 14.0 13.0 12.0 11.0 10.0 9.0 8.0 7.0 6.0 0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 Load current ILoad [mA] 67/74 PEDL9051G-01 OKI Semiconductor ML9051G EQUIVALENT CIRCUIT FOR EVALUATING POWER-UP STABILIZATION TIME IN COG MOUNTING VIN = 5.0 V R VIN R VSS C1 - C1 - + R VC4 + R VS2- R VS1- C1 - + OPEN R VC5 + VC3 + ML9051G Chip 200 V5 + C2 - V4 + R VC6 + Dummy 200 + C2 - V3 R VOUT 200 + V2 + C2 - 200 C2 - V1 200 + C1 - Equivalent circuit to 3-time voltage multiplier with trace resistances external to the COG-mounted chip VIN = 4.5 V R VIN R VSS V1 200 C1 + - C1 -+ C1 - C1 - + + 200 V2 C2 + - R VOUT R VC6 + Dummy R VC4 + R R VS1 - VS2 - V3 200 C2 + - V4 200 C2 + - V5 200 C2 + - C1 - + R VC5 + R VC3 + ML9051G Chip Equivalent circuit to 4-time voltage multiplier with trace resistances external to the COG-mounted chip 68/74 PEDL9051G-01 OKI Semiconductor ML9051G REFERENCE DATA (The rise time until V1-V5 is stabilized when command "2F" is input after power-on in COG mounting.) 3-time voltage multiplication, normal mode Reference value of V1-V5 rise stabilization time in ML9051G COG mounting Conditions: VIN = 5 V, 3-time voltage multiplication, V1 = 12 V, trace resistance external to COG-mounted chip R = 150, normal mode, 1/8 bias, Ta = -40C to +85C Note: Display is forbidden for 300 ms maximum on the ML9051G circuit. 700 Parameter = smoothing capacitor C2 600 C2 = 0.47 F 500 C2 = 1 F Rise time [ms] 400 300 200 100 0 0 0.5 1 1.5 2 2.5 3 3.5 Value of voltage multiplier capacitor C1 [F] 4 4.5 5 3-time voltage multiplication, high-power mode Reference value of V1-V5 rise stabilization time in ML9051G COG mounting Conditions: VIN = 5 V, 3-time voltage multiplication, V1 = 12 V, trace resistance external to COG-mounted chip R = 150, high-power mode, 1/8 bias, Ta = -40C to +85C Note: Display is forbidden for 300 ms maximum on the ML9051G circuit. 700 600 Parameter = smoothing capacitor C2 C2 = 0.47 F 500 C2 = 1 F Rise time [ms] 400 300 200 100 0 0 0.5 1 1.5 2 2.5 3 3.5 Value of voltage multiplier capacitor C1 [F] 4 4.5 5 69/74 PEDL9051G-01 OKI Semiconductor ML9051G REFERENCE DATA (The rise time until V1-V5 is stabilized when command "2F" is input after power-on in COG mounting.) 3-time voltage multiplication, normal mode Reference value of V1-V5 rise stabilization time in ML9051G COG mounting Conditions: VIN = 5 V, 3-time voltage multiplication, normal mode, 1/8 bias, Ta = -40C to +85C, voltage multiplier capacitor C1 = 3.3 F, smoothing capacitor C2 = 1 F 500 450 Parameter: trace resistance external to COG-mounted chip 400 R = 100 350 300 Rise time [ms] 250 200 150 100 50 0 10.5 R = 150 R = 200 11 11.5 12 V1 voltage [V] 12.5 13 13.5 3-time voltage multiplication, high-power mode Reference value of V1-V5 rise stabilization time in ML9051G COG mounting Conditions: VIN = 5 V, 3-time voltage multiplication, high-power mode, 1/8 bias, Ta = -40C to +85C, voltage multiplier capacitor C1 = 3.3 F, smoothing capacitor C2 = 1 F 500 450 400 R = 100 350 300 Rise time [ms] 250 200 150 100 50 0 10.5 R = 150 R = 200 Parameter: trace resistance external to COG-mounted chip 11 11.5 12 V1 voltage [V] 12.5 13 13.5 70/74 PEDL9051G-01 OKI Semiconductor ML9051G REFERENCE DATA (The rise time until V1-V5 is stabilized when command "2F" is input after power-on in COG mounting.) 4-time voltage multiplication, normal mode Reference value of V1-V5 rise stabilization time in ML9051G COG mounting Conditions: VIN = 4.5 V, 4-time voltage multiplication, V1 = 12 V, trace resistance external to COG-mounted chip R = 150, normal mode, 1/8 bias, Ta = -40C to +85C Note: Display is forbidden for 300 ms maximum on the ML9051G circuit. 900 800 Parameter = smoothing capacitor C2 700 C2 = 0.47 F 600 Rise time [ms] 500 400 300 200 100 0 C2 = 1 F 0 0.5 1 1.5 2 2.5 3 3.5 Value of voltage multiplier capacitor C1 [F] 4 4.5 5 4-time voltage multiplication, high-power mode Reference value of V1-V5 rise stabilization time in ML9051G COG mounting Conditions: VIN = 4.5 V, 4-time voltage multiplication, V1 = 12 V, trace resistance external to COG-mounted chip R = 150, high-power mode, 1/8 bias, Ta = -40C to +85C Note: Display is forbidden for 300 ms maximum on the ML9051G circuit. 900 800 Parameter = smoothing capacitor C2 700 C2 = 0.47 F 600 Rise time [ms] 500 400 300 200 100 0 0 0.5 1 1.5 2 2.5 3 3.5 Value of voltage multiplier capacitor C1 [F] 4 4.5 5 C2 = 1 F 71/74 PEDL9051G-01 OKI Semiconductor ML9051G REFERENCE DATA (The rise time until V1-V5 is stabilized when command "2F" is input after power-on in COG mounting.) 4-time voltage multiplication, normal mode Reference value of V1-V5 rise stabilization time in ML9051G COG mounting Conditions: VIN = 4.5 V, 4-time voltage multiplication, normal mode, 1/8 bias, Ta = -40C to +85C, voltage multiplier capacitor C1 = 3.3 F, smoothing capacitor C2 = 1 F 500 450 400 350 300 Rise time [ms] 250 200 150 100 50 0 10.5 11 11.5 12 12.5 V1 voltage [V] 13 13.5 14 14.5 Parameter: trace resistance external to COG-mounted chip R = 100 R = 150 R = 200 4-time voltage multiplication, high-power mode Reference value of V1-V5 rise stabilization time in ML9051G COG mounting Conditions: VIN = 4.5 V, 4-time voltage multiplication, high-power mode, 1/8 bias, Ta = -40C to +85C, voltage multiplier capacitor C1 = 3.3 F, smoothing capacitor C2 = 1 F 500 450 Parameter: trace resistance external to COG-mounted chip 400 R = 100 350 300 Rise time [ms] 250 200 150 100 50 0 10.5 11 11.5 12 12.5 V1 voltage [V] 13 13.5 14 14.5 R = 150 R = 200 72/74 PEDL9051G-01 OKI Semiconductor ML9051G REVISION HISTORY Document No. PEDL9051G-01 Date Jul. 23, 2002 Page Previous Current Edition Edition - - Description Preliminary first edition 73/74 PEDL9051G-01 OKI Semiconductor ML9051G NOTICE 1. The information contained herein can change without notice owing to product and/or technical improvements. Before using the product, please make sure that the information being referred to is up-to-date. 2. The outline of action and examples for application circuits described herein have been chosen as an explanation for the standard action and performance of the product. When planning to use the product, please ensure that the external conditions are reflected in the actual circuit, assembly, and program designs. When designing your product, please use our product below the specified maximum ratings and within the specified operating ranges including, but not limited to, operating voltage, power dissipation, and operating temperature. Oki assumes no responsibility or liability whatsoever for any failure or unusual or unexpected operation resulting from misuse, neglect, improper installation, repair, alteration or accident, improper handling, or unusual physical or electrical stress including, but not limited to, exposure to parameters beyond the specified maximum ratings or operation outside the specified operating range. Neither indemnity against nor license of a third party's industrial and intellectual property right, etc. is granted by us in connection with the use of the product and/or the information and drawings contained herein. No responsibility is assumed by us for any infringement of a third party's right which may result from the use thereof. The products listed in this document are intended for use in general electronics equipment for commercial applications (e.g., office automation, communication equipment, measurement equipment, consumer electronics, etc.). These products are not authorized for use in any system or application that requires special or enhanced quality and reliability characteristics nor in any system or application where the failure of such system or application may result in the loss or damage of property, or death or injury to humans. Such applications include, but are not limited to, traffic and automotive equipment, safety devices, aerospace equipment, nuclear power control, medical equipment, and life-support systems. Certain products in this document may need government approval before they can be exported to particular countries. The purchaser assumes the responsibility of determining the legality of export of these products and will take appropriate and necessary steps at their own expense for these. No part of the contents contained herein may be reprinted or reproduced without our prior permission. Copyright 2002 Oki Electric Industry Co., Ltd. 3. 4. 5. 6. 7. 8. 74/74 |
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